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https://github.com/oopuuu/zTC1.git
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89 lines
1.8 KiB
Plaintext
89 lines
1.8 KiB
Plaintext
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/*
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* MT7637 CM4 Loader Memory Map
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*
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*/
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ENTRY(ResetISR)
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MEMORY
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{
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ROM_CODE (rx) : ORIGIN = 0x0, LENGTH = 0x00005000 /* 20k */
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TCMRAM (rwx) : ORIGIN = 0x00100000, LENGTH = 0x00010000 /* 64k */
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XIP_LOADER_CODE (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 /* 32k */
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XIP_CODE (rx) : ORIGIN = 0x1006C000, LENGTH = 0x00040000 /* 256k */
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SYSRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 /* 256k */
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SYSRAM_DATA_BSS (rw) : ORIGIN = 0x2003C000, LENGTH = 0x00004000 /* 16k for loader and rom's data section */
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/* for debug/temperoary */
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SYSRAM_MIDDLE (rw) : ORIGIN = 0x20020000, LENGTH = 0x00020000
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/* XIP(0x10000000) remapping by SYSRAM bus*/
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XIP_SYSRAM_CODE (rx) : ORIGIN = 0x30000000, LENGTH = 0x00100000 /* 1MB */
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}
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SECTIONS
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{
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. = ORIGIN(SYSRAM);
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_text_lma_start = LOADADDR(.text);
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.text :
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{
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_text_start = .;
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*(.except_vectors)
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*(.reset_isr)
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*(.text .text.*)
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*(.rodata .rodata.*)
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_text_end = .;
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} > SYSRAM AT > XIP_LOADER_CODE
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. = ALIGN(4);
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_data_lma_start = LOADADDR(.data);
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.data :
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{
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_data_start = .;
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KEEP(*(.ramTEXT))
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. = ALIGN(4);
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*(.data .data.*)
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_data_end = .;
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} > SYSRAM
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. = ALIGN(4);
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.bss :
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{
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_bss_start = .;
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*(.bss .bss.*)
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*(COMMON)
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_bss_end = .;
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} > SYSRAM
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. = ALIGN(4);
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.heap :
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{
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__end__ = .;
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end = __end__;
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*(.heap*)
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__HeapLimit = .;
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}
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}
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/* Declare libc Heap to start at end of allocated RAM */
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PROVIDE( _heap = __end__ );
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/* End of the heap is top of RAM, aligned 8 byte */
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PROVIDE( _eheap = ALIGN( ORIGIN( SYSRAM ) + LENGTH( SYSRAM ) - 8, 8 ) );
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