mirror of
https://github.com/oopuuu/zTC1.git
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133 lines
2.8 KiB
INI
133 lines
2.8 KiB
INI
#
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# Copyright (C)
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# All Rights Reserved.
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#
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# OpenOCD config script for MX1290
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source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]
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set CHIP_RAM_START 0x10005000
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# yhb changed to support SWD
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proc swj_newdap {chip tag args} {
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if [using_hla] {
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eval hla newtap $chip $tag $args
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} elseif [using_jtag] {
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eval jtag newtap $chip $tag $args
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} elseif [using_swd] {
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eval swd newdap $chip $tag $args
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}
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}
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# yhb set SWD
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transport select swd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME MX1290
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 32MHz,
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# and it has been found not to work reliably at 5MHz,
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# so use F_JTAG = 3MHz
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adapter_khz 2000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys $CHIP_RAM_START -work-area-size $_WORKAREASIZE -work-area-backup 0
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if { [info exists CONFIG_FLASH] } {
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flash bank wm0.flash mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
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flash bank wm1.flash mrvlqspi 0x400000 0 0 0 $_TARGETNAME 0x46090000
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}
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#gdb_report_data_abort enable
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proc wdt_off {} {
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#void BKUP_Set(u32 DwordIdx, u32 BitMask);
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#call BKUP_Set(BKUP_REG1, BIT_FORCE_WDT_DISABLE)
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#set param 1 = BKUP_REG1
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reg r0 0x00000001
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#set param 2 = BIT_FORCE_WDT_DISABLE
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reg r1 0x00000001
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#set return address = reset handler
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reg lr 0x00000101
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#set pc = BKUP_Set() addrress
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reg pc 0x0000228d
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#set breakpoint at reset handler
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bp 0x00000100 0x02
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#run
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resume
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sleep 1
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#void WDG_Cmd(u32 NewState);
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#call WDG_Cmd(DISABLE)
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#set param 1 = DISABLE
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reg r0 0x00000000
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#set return address = reset handler
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reg lr 0x00000101
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#set pc = WDG_Cmd() addrress
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reg pc 0x0000d83d
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#run
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resume
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sleep 1
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#remove breakpoint
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rbp 0x00000100
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halt
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}
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$_TARGETNAME configure -event gdb-attach {
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reset halt
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wdt_off
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}
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#shutdown OpenOCD daemon when gdb detaches
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$_TARGETNAME configure -event gdb-detach {
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resume
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shutdown
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}
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$_TARGETNAME configure -event reset-end {
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mww 0x40000210 0x00010113
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mww 0x40000214 0x00000000
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}
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#yhb set the reset is done internally over the SWD channel with no pins used.
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reset_config none separate
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config vectreset
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