#
# Copyright (C) 
# All Rights Reserved.
#

# OpenOCD config script for MX1290
source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]

set CHIP_RAM_START   0x10005000

# yhb changed to support SWD
proc swj_newdap {chip tag args} {
 if [using_hla] {
     eval hla newtap $chip $tag $args
 } elseif [using_jtag] {
     eval jtag newtap $chip $tag $args
 } elseif [using_swd] {
     eval swd newdap $chip $tag $args
 }
}

# yhb set SWD
transport select swd

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME MX1290
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

# Work-area is a space in RAM used for flash programming
# By default use 16kB
if { [info exists WORKAREASIZE] } {
   set  _WORKAREASIZE $WORKAREASIZE
} else {
   set  _WORKAREASIZE 0x4000
}

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 32MHz,
# and it has been found not to work reliably at 5MHz,
# so use F_JTAG = 3MHz
adapter_khz 2000

adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}


#jtag scan chain
if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x4ba00477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID


set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME 

$_TARGETNAME configure -work-area-phys $CHIP_RAM_START -work-area-size $_WORKAREASIZE -work-area-backup 0
if { [info exists CONFIG_FLASH] } {
   flash bank wm0.flash mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
   flash bank wm1.flash mrvlqspi 0x400000 0 0 0 $_TARGETNAME 0x46090000
}

#gdb_report_data_abort enable

proc wdt_off {} {
#void BKUP_Set(u32 DwordIdx, u32 BitMask);
#call BKUP_Set(BKUP_REG1, BIT_FORCE_WDT_DISABLE)
#set param 1 = BKUP_REG1
  reg r0 0x00000001
#set param 2 = BIT_FORCE_WDT_DISABLE
  reg r1 0x00000001
#set return address = reset handler
  reg lr 0x00000101
#set pc = BKUP_Set() addrress
  reg pc 0x0000228d
#set breakpoint at reset handler
  bp 0x00000100 0x02
#run
  resume
  sleep 1

#void WDG_Cmd(u32 NewState);
#call WDG_Cmd(DISABLE)
#set param 1 = DISABLE
  reg r0 0x00000000
#set return address = reset handler
  reg lr 0x00000101
#set pc = WDG_Cmd() addrress
  reg pc 0x0000d83d
#run
  resume
  sleep 1

#remove breakpoint
  rbp 0x00000100
  halt
}

$_TARGETNAME configure -event gdb-attach {
    reset halt
    wdt_off
}

#shutdown OpenOCD daemon when gdb detaches
$_TARGETNAME configure -event gdb-detach {
  resume
  shutdown 
}

$_TARGETNAME configure -event reset-end {
  mww 0x40000210  0x00010113
  mww 0x40000214  0x00000000
}

#yhb set the reset is done internally over the SWD channel with no pins used.
reset_config none separate 

# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config vectreset