修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置

mico-os/makefiles/OpenOCD/mw3xx/mw3xx.cfg

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+source [find mico-os/makefiles/OpenOCD/mw3xx/wmcore.cfg]
+
+### chip_id() -- get chip revision id
+
+proc chip_id { } {
+	# make sure the CPU is stopped and in a known state
+        reset halt
+
+	# Update this array for each unique chip id
+	array set chip_id_array {
+		0x00000001 "mc200"
+		0x88110841 "mc200"
+		0x88130A40 "mw300"
+		0x88130A41 "mw300"
+	}
+
+	# read chip revision id register
+	mem2array chip_id 32 0x480b0000 1
+
+	foreach {chip_id_val chip_name} [array get chip_id_array] {
+		if { $chip_id(0) == $chip_id_val } {
+			echo [format "Chip id 0x%08x detected" $chip_id(0)]
+			puts -nonewline $chip_name
+			return
+		}
+	}
+
+	# chip id not known, print chip id for diagnostics
+	echo [format "Unknown chip id 0x%08x" $chip_id(0)]
+	puts -nonewline "unknown"
+}
+
+### chip_fix() -- do chip specific fixup
+
+proc chip_fixup { } {
+	# read chip revision id register
+	mem2array chip_id 32 0x480b0000 1
+
+	# Fix for mw300
+	if { $chip_id(0) == 0x88130A41 } {
+		# Change system clock source to RC32M
+		mwb 0x480a0018 1
+		# Reset WLAN
+		mwb 0x480a0118 0
+	}
+}
+
+### program_image() -- program flash using openocd flash commands
+#
+# 1. Reset and halt processor in a known state
+# 2. Erase the requested flash region and write $filename data at $offset
+#    in the flash
+
+proc program_image { offset filename } {
+	# make sure the CPU is stopped and in a known state
+        reset halt
+
+	# do chip fixup if any
+	chip_fixup
+
+	# erase the flash region and write file data at the offset
+	flash write_image erase $filename $offset
+}
+
+### load() -- load any generic application axf image to ram and run ###
+#
+# 1. Reset and halt processor in a known state
+# 2. Load axf image into internal ram of target device
+# 3. Verify loaded axf image
+# 4. Pass control to loaded image using its entry point address
+#
+# NOTE: Entry point address of axf image can be found using
+# command: readelf -h <image>
+
+proc load { img entry_point } {
+	# make sure the CPU is stopped and in a known state
+        reset halt
+
+	# do chip fixup if any
+	chip_fixup
+
+        # load the axf image
+        load_image $img
+	# verify the loaded image
+        verify_image $img
+
+        # execute the loaded image
+        resume $entry_point
+}
+
+### sh_load() -- load flashprog.axf (flash tool) image to ram and run ###
+#
+# 1. Reset and halt processor in a known state
+# 2. Enable arm semihosting
+# 3. Load axf image into internal ram of target device
+# 4. Verify loaded axf image
+# 5. Pass control to loaded image using its entry point address
+#
+# NOTE: Entry point address of axf image can be found using
+# command: readelf -h <image>
+
+proc sh_load { img entry_point } {
+	# make sure the CPU is stopped and in a known state
+        reset halt
+ 
+	# do chip fixup if any
+	chip_fixup
+
+        # load the axf image
+        load_image $img
+	# verify the loaded image
+        verify_image $img
+
+        # enable semihosting by default (needed for flashprog)
+        arm semihosting enable
+
+	# attach handler for halt
+	wmcore.cpu configure -event halted {
+		echo "Flashprog Complete"
+		shutdown
+	}
+
+        # execute the loaded image
+	resume $entry_point
+}

mico-os/makefiles/OpenOCD/mw3xx/mw3xx_gdb_jtag.cfg

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+#
+#  UNPUBLISHED PROPRIETARY SOURCE CODE
+#  Copyright (c) 2016 MXCHIP Inc.
+#
+#  The contents of this file may not be disclosed to third parties, copied or
+#  duplicated in any form, in whole or in part, without the prior written
+#  permission of MXCHIP Corporation.
+#
+# default ports
+telnet_port 4444
+gdb_port 3333
+gdb_memory_map enable
+
+init

mico-os/makefiles/OpenOCD/mw3xx/wmcore.cfg

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+#
+# Copyright (C) 2008-2014, Marvell International Ltd.
+# All Rights Reserved.
+#
+
+# OpenOCD config script for mc200 and mw300
+
+set CHIP_RAM_START   0x00100000
+
+# yhb changed to support SWD
+proc swj_newdap {chip tag args} {
+ if [using_hla] {
+     eval hla newtap $chip $tag $args
+ } elseif [using_jtag] {
+     eval jtag newtap $chip $tag $args
+ } elseif [using_swd] {
+     eval swd newdap $chip $tag $args
+ }
+}
+
+# yhb set SWD
+transport select swd
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME wmcore
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 32MHz,
+# and it has been found not to work reliably at 5MHz,
+# so use F_JTAG = 3MHz
+adapter_khz 2000
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+jtag_ntrst_delay 100
+}
+
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4ba00477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME -rtos auto
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+if { [info exists CONFIG_FLASH] } {
+   flash bank wm0.flash mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
+   flash bank wm1.flash mrvlqspi 0x400000 0 0 0 $_TARGETNAME 0x46090000
+}
+
+#gdb_report_data_abort enable
+
+$_TARGETNAME configure -event gdb-attach {
+    echo "MiCO: GDB ATTACHED"
+    reset halt
+    mww 0x480C0100 0x00c89346
+}
+
+#shutdown OpenOCD daemon when gdb detaches
+$_TARGETNAME configure -event gdb-detach { reset halt; mww 0x480C0100 0x0; sleep 5; resume; shutdown }
+
+#yhb copy from stm32f4x.cfg
+#reset_config srst_nogate
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m reset_config sysresetreq