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https://github.com/oopuuu/zTC1.git
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91 lines
2.1 KiB
INI
91 lines
2.1 KiB
INI
#
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# Copyright (C) 2008-2014, Marvell International Ltd.
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# All Rights Reserved.
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#
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# OpenOCD config script for mc200 and mw300
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set CHIP_RAM_START 0x00100000
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# yhb changed to support SWD
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proc swj_newdap {chip tag args} {
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if [using_hla] {
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eval hla newtap $chip $tag $args
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} elseif [using_jtag] {
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eval jtag newtap $chip $tag $args
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} elseif [using_swd] {
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eval swd newdap $chip $tag $args
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}
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}
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# yhb set SWD
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transport select swd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME wmcore
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 32MHz,
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# and it has been found not to work reliably at 5MHz,
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# so use F_JTAG = 3MHz
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adapter_khz 2000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME -rtos auto
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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if { [info exists CONFIG_FLASH] } {
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flash bank wm0.flash mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
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flash bank wm1.flash mrvlqspi 0x400000 0 0 0 $_TARGETNAME 0x46090000
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}
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#gdb_report_data_abort enable
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$_TARGETNAME configure -event gdb-attach {
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echo "MiCO: GDB ATTACHED"
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reset halt
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mww 0x480C0100 0x00c89346
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}
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#shutdown OpenOCD daemon when gdb detaches
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$_TARGETNAME configure -event gdb-detach { reset halt; mww 0x480C0100 0x0; sleep 5; resume; shutdown }
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#yhb copy from stm32f4x.cfg
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#reset_config srst_nogate
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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