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fix pinout

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Septs
2021-02-13 09:39:28 +08:00
parent 0bc4dc35cb
commit 2d573b25d6
2 changed files with 13 additions and 2 deletions
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2
PINOUT/SPI-30PIN.md
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@@ -26,7 +26,7 @@
| 8 | I | RES# | Global reset pin | [SPI][spi], [RES#][resn] |
| 9 | O | BUSY | Busy state output | [BUSY][busy] |
| 10 | I | BS<sub>1</sub> | Bus selection | [BS1][bs1] |
| 11 | PWR | V<sub>DD</sub> | (SPI VDD) Digital power input | |
| 11 | PWR | V<sub>DD</sub>IO | (SPI VDD) Digital power input | |
| 12 | PWR | V<sub>DL</sub> | Negative source driving voltage | Driving voltage |
| 13 | PWR | V<sub>DH</sub> | Positive source driving voltage | Driving voltage |
| 14 | PWR | V<sub>GH</sub> | Positive gate driving voltage | Driving voltage |

13
PINOUT/SPI-60PIN.md
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@@ -29,7 +29,7 @@
| 11 | I | CS# | S1/S2 | (SPI SS) Chip select | [SPI][spi] |
| 12 | I | SCL | | (SPI SCLK) Serial clock | [SPI][spi] |
| 13 | I/O | SDA | | (SPI MOSI) Serial data in | [SPI][spi] |
| 14 | I/O | L<sup>SYNC</sup> | M1/M2 | 2 + 2 Cascade Sync Signal | |
| 14 | I/O | L/R<sup>SYNC</sup> | M1/M2 | 2 + 2 Cascade Sync Signal | |
| 15 | I/O | M1/M2<sup>SYNC</sup> | M1/M2 | 2 + 2 Cascade Sync Signal | |
| 16 | I/O | M2/M1<sup>SYNC</sup> | M1/M2 | 2 + 2 Cascade Sync Signal | |
| 17 | PWR | V<sub>DD</sub>IO | M1/M2 | (SPI VCC) IO voltage supply | |
@@ -54,3 +54,14 @@
[rese]: SPI-24PIN.md#rese
[resn]: SPI-24PIN.md#resn
[spi]: SPI-24PIN.md#spi
## Cascade
| M1 | PIN# | PIN# | M2 |
| -------------------: | ---: | :--- | :------------------- |
| SCL | 12 | 12 | SCL |
| SDA | 13 | 13 | SDA |
| L<sup>SYNC</sup> | 14 | 16 | M2/M1<sup>SYNC</sup> |
| M1/M2<sup>SYNC</sup> | 15 | 15 | M2/M1<sup>SYNC</sup> |
| M2/M1<sup>SYNC</sup> | 16 | 14 | R<sup>SYNC</sup> |
| V<sub>COM</sub> | 26 | 26 | V<sub>COM</sub> |