mirror of
https://github.com/oopuuu/zTC1.git
synced 2025-12-17 23:48:13 +08:00
821 lines
22 KiB
C
821 lines
22 KiB
C
/*
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* Copyright 2016, MXCHIP.
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* All Rights Reserved.
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*/
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/*
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* uart.c: mxchip driver for UART
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*/
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#include <board.h>
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#include <wmtypes.h>
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#include <wmstdio.h>
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#include <mdev_uart.h>
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//#include <wm_os.h>
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#include <pwrmgr.h>
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#include <mdev_dma.h>
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#include <wmassert.h>
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#include <system-work-queue.h>
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#include "common.h"
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#include "mico_platform.h"
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#define DISABLE_DMA
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#ifdef DISABLE_DMA
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#define NUM_UART_PORTS 3
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#define UART_IRQn_BASE UART0_IRQn
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#define UART_INT_BASE INT_UART0
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#ifdef NO_MICO_RTOS
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#define os_thread_relinquish()
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#endif
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static void (*uart_8bit_cb_p[NUM_UART_PORTS]) ();
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static void (*uart_9bit_cb_p[NUM_UART_PORTS]) ();
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#define SET_RX_BUF_SIZE(uart_data_p, size) \
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uart_data_p->rx_ringbuf.buf_size = size
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#define GET_RX_BUF_SIZE(uart_data_p) (uart_data_p->rx_ringbuf.buf_size)
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#define SET_DMA_BLK_SIZE(uart_data_p, size) \
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uart_data_p->rx_ringbuf.dma_block_size = size
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#define GET_DMA_BLK_SIZE(uart_data_p) (uart_data_p->rx_ringbuf.dma_block_size)
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#define DEFINE_UART_CB(id, mode) \
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static void \
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uart ## id ## _ ## mode ## bit_cb() {\
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uart_ ## mode ## bit_cb(id); }
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#define GET_UART_CB(id, mode) uart ## id ## _ ## mode ## bit_cb
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extern platform_uart_t platform_uart_peripherals[];
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extern platform_uart_driver_t platform_uart_drivers[];
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/* UART callback functions */
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static void uart_8bit_cb(int port_num)
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{
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uint8_t recv_byte, i;
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platform_uart_driver_t* driver = NULL;
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for ( i = 0; i < MICO_UART_MAX; i++ ) {
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if ( platform_uart_peripherals[i].port_id == port_num ) {
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driver = &platform_uart_drivers[i];
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break;
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}
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}
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if ( driver == NULL ) return;
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/* Receive new data */
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while (UART_GetLineStatus(port_num, UART_LINESTATUS_DR) == SET) {
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if (ring_buffer_is_full(driver->rx_ring_buffer) == 0) {
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recv_byte = UART_ReceiveData(port_num);
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ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
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if ( ( driver->rx_size > 0 ) &&
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( ring_buffer_used_space( driver->rx_ring_buffer) >= driver->rx_size ) ) {
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mico_rtos_set_semaphore( &driver->rx_complete );
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driver->rx_size = 0;
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}
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} else {
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/* Rx Buffer is full, discard received data */
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if (driver->flow_control != FLOW_CONTROL_DISABLED_DRV) {
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/* We need to mask the interrupt till the data
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is read; otherwise we keep getting
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data-ready interrupt infinitely */
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UART_IntMask(port_num, UART_INT_RDA, MASK);
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return;
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} else {
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UART_ReceiveData(port_num);
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}
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}
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}
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}
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static void uart_9bit_cb(int port_num)
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{
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uint16_t data;
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platform_uart_driver_t* driver = &platform_uart_drivers[port_num];
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uint8_t recv_byte;
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/* Receive new data */
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while (UART_GetLineStatus(port_num, UART_LINESTATUS_DR) == SET) {
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if (ring_buffer_free_space(driver->rx_ring_buffer) > 1) {
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data = UART_Receive9bits(port_num);
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recv_byte = (uint8_t) ((data >> 8) & 0x01);
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ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
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recv_byte = (uint8_t) (data & 0xFF);
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ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
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if ( ( driver->rx_size > 0 ) &&
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( ring_buffer_used_space( driver->rx_ring_buffer ) >= driver->rx_size ) ) {
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mico_rtos_set_semaphore( &driver->rx_complete );
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driver->rx_size = 0;
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}
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} else {
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/* Rx Buffer is full, discard received data */
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if (driver->flow_control != FLOW_CONTROL_DISABLED_DRV) {
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/* We need to mask the interrupt till the data
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is read; otherwise we keep getting
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data-ready interrupt infinitely */
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UART_IntMask(port_num, UART_INT_RDA, MASK);
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return;
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} else {
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UART_Receive9bits(port_num);
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}
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}
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}
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}
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DEFINE_UART_CB(0, 8)
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DEFINE_UART_CB(1, 8)
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DEFINE_UART_CB(0, 9)
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DEFINE_UART_CB(1, 9)
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#if (NUM_UART_PORTS > 2)
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DEFINE_UART_CB(2, 8)
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DEFINE_UART_CB(2, 9)
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#if (NUM_UART_PORTS > 3)
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DEFINE_UART_CB(3, 8)
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DEFINE_UART_CB(3, 9)
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#endif
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#endif
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static void fill_cb_array()
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{
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uart_8bit_cb_p[0] = GET_UART_CB(0, 8);
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uart_8bit_cb_p[1] = GET_UART_CB(1, 8);
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uart_9bit_cb_p[0] = GET_UART_CB(0, 9);
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uart_9bit_cb_p[1] = GET_UART_CB(1, 9);
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#if (NUM_UART_PORTS > 2)
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uart_8bit_cb_p[2] = GET_UART_CB(2, 8);
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uart_9bit_cb_p[2] = GET_UART_CB(2, 9);
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#if (NUM_UART_PORTS > 3)
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uart_8bit_cb_p[3] = GET_UART_CB(3, 8);
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uart_9bit_cb_p[3] = GET_UART_CB(3, 9);
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#endif
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#endif
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}
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OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
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//int platform_uart_init(int port_id, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer)
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{
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UART_CFG_Type uartcfg;
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UART_FifoCfg_Type fifocfg;
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uint32_t port_id = peripheral->port_id;
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//platform_uart_driver_t* driver;
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//sys_work_queue_init();
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if (port_id < 0 || port_id >= NUM_UART_PORTS) {
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UART_LOG("Port %d not enabled\r\n", port_id);
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return -1;
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}
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fill_cb_array();
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//driver = &uart_drivers[port_id];
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driver->id = port_id;
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switch (driver->id) {
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case UART0_ID:
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CLK_SetUARTClkSrc(CLK_UART_ID_0, CLK_UART_FAST);
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CLK_ModuleClkEnable(CLK_UART0);
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break;
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case UART1_ID:
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CLK_SetUARTClkSrc(CLK_UART_ID_1, CLK_UART_SLOW);
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CLK_ModuleClkEnable(CLK_UART1);
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break;
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case UART2_ID:
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CLK_SetUARTClkSrc(CLK_UART_ID_2, CLK_UART_SLOW);
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CLK_ModuleClkEnable(CLK_UART2);
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break;
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}
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if (optional_ring_buffer != NULL){
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/* Note that the ring_buffer should've been initialised first */
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driver->rx_ring_buffer = optional_ring_buffer;
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} else {
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uint8_t *pbuf;
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pbuf = malloc(512);
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ring_buffer_init(driver->rx_ring_buffer, pbuf, 512);
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}
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/* Initialize the UART port's mdev structure */
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driver->rx_size = 0;
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driver->tx_size = 0;
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driver->last_transmit_result = kNoErr;
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driver->last_receive_result = kNoErr;
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uartcfg.baudRate = config->baud_rate;
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uartcfg.stickyParity = DISABLE;
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fifocfg.fifoEnable = ENABLE;
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switch (config->data_width) {
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case DATA_WIDTH_5BIT:
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uartcfg.dataBits = UART_DATABITS_5;
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break;
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case DATA_WIDTH_6BIT:
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uartcfg.dataBits = UART_DATABITS_6;
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break;
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case DATA_WIDTH_7BIT:
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uartcfg.dataBits = UART_DATABITS_7;
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break;
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case DATA_WIDTH_8BIT:
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uartcfg.dataBits = UART_DATABITS_8;
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break;
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case DATA_WIDTH_9BIT:
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uartcfg.dataBits = UART_DATABITS_8;
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uartcfg.parity = UART_PARITY_EVEN;
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uartcfg.stickyParity = DISABLE;
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fifocfg.fifoEnable = DISABLE;
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break;
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default:
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uartcfg.dataBits = UART_DATABITS_8;
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break;
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}
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switch ( config->parity )
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{
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case NO_PARITY:
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uartcfg.parity = UART_PARITY_NONE;
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break;
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case EVEN_PARITY:
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uartcfg.parity = UART_PARITY_EVEN;
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break;
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case ODD_PARITY:
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uartcfg.parity = UART_PARITY_ODD;
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break;
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default:
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uartcfg.parity = UART_PARITY_NONE;
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break;
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}
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if (config->flow_control != FLOW_CONTROL_DISABLED) {
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fifocfg.autoFlowControl = ENABLE;
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} else {
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fifocfg.autoFlowControl = DISABLE;
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}
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if ( config->stop_bits == STOP_BITS_1 )
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UART_SetStopBits(port_id, UART_STOPBITS_1);
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else
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UART_SetStopBits(port_id, UART_STOPBITS_2);
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fifocfg.rxFifoLevel = UART_RXFIFO_BYTE_1;
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fifocfg.txFifoLevel = UART_TXFIFO_HALF_EMPTY;
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fifocfg.peripheralBusType = UART_PERIPHERAL_BITS_8;
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fifocfg.fifoDmaEnable = DISABLE;
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UART_Disable(driver->id);
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UART_Enable(driver->id);
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UART_Init(driver->id, &uartcfg);
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UART_FifoConfig(driver->id, &fifocfg);
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install_int_callback(UART_INT_BASE + driver->id,
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UART_INT_RDA,
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(config->data_width == DATA_WIDTH_9BIT) ?
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uart_9bit_cb_p[driver->id] :
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uart_8bit_cb_p[driver->id]);
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NVIC_EnableIRQ(UART_IRQn_BASE + driver->id);
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NVIC_SetPriority(UART_IRQn_BASE + driver->id, 0xf);
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UART_IntMask(driver->id, UART_INT_RDA, UNMASK);
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/* Configure the pinmux for uart pins */
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board_uart_pin_config(driver->id);
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mico_rtos_init_semaphore( &driver->tx_complete, 1 );
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mico_rtos_init_semaphore( &driver->rx_complete, 1 );
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mico_rtos_init_semaphore( &driver->sem_wakeup, 1 );
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mico_rtos_init_mutex ( &driver->tx_mutex );
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return WM_SUCCESS;
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}
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//uint32_t mico_get_time_no_os(void)
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//{
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// return os_total_ticks_get();
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//}
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OSStatus platform_uart_receive_bytes( platform_uart_driver_t* driver, uint8_t* data_in, uint32_t expected_data_size, uint32_t timeout_ms )
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{
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OSStatus err = kNoErr;
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if (( data_in == NULL ) || ( expected_data_size == 0 )) {
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err = kParamErr;
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goto exit;
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}
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while (expected_data_size != 0)
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{
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uint32_t transfer_size = MIN( driver->rx_ring_buffer->size/2, expected_data_size );
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/* Check if ring buffer already contains the required amount of data. */
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if ( transfer_size > ring_buffer_used_space( driver->rx_ring_buffer ) )
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{
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/* Set rx_size and wait in rx_complete semaphore until data reaches rx_size or timeout occurs */
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driver->rx_size = transfer_size;
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if ( mico_rtos_get_semaphore( &driver->rx_complete, timeout_ms) != kNoErr )
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{
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driver->rx_size = 0;
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return kTimeoutErr;
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}
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/* Reset rx_size to prevent semaphore being set while nothing waits for the data */
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driver->rx_size = 0;
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}
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expected_data_size -= transfer_size;
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// Grab data from the buffer
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do
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{
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uint8_t* available_data;
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uint32_t bytes_available;
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ring_buffer_get_data( driver->rx_ring_buffer, &available_data, &bytes_available );
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bytes_available = MIN( bytes_available, transfer_size );
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memcpy( data_in, available_data, bytes_available );
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transfer_size -= bytes_available;
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data_in = ( (uint8_t*) data_in + bytes_available );
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ring_buffer_consume( driver->rx_ring_buffer, bytes_available );
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} while ( transfer_size != 0 );
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}
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if ( expected_data_size != 0 )
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{
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return kGeneralErr;
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}
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else
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{
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return kNoErr;
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}
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exit:
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//platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_uart_transmit_bytes( platform_uart_driver_t* driver, const uint8_t* data_out, uint32_t size )
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//OSStatus platform_uart_transmit_bytes( int port_id, const uint8_t* data_out, uint32_t size )
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{
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int i;
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if (driver->tx_mutex)
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mico_rtos_lock_mutex( &driver->tx_mutex );
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for(i=0; i<size; i++) {
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while (UART_GetLineStatus(driver->id,
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UART_LINESTATUS_TDRQ) != SET) {
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os_thread_relinquish();
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}
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UART_SendData(driver->id, data_out[i]);
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}
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if (driver->tx_mutex)
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mico_rtos_unlock_mutex( &driver->tx_mutex );
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return kNoErr;
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}
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uint32_t platform_uart_get_length_in_buffer( platform_uart_driver_t* driver )
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{
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return ring_buffer_used_space( driver->rx_ring_buffer );
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}
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OSStatus platform_uart_deinit( platform_uart_driver_t* driver )
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{
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mico_rtos_deinit_semaphore( &driver->rx_complete );
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mico_rtos_deinit_semaphore( &driver->tx_complete );
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mico_rtos_deinit_semaphore( &driver->sem_wakeup );
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mico_rtos_deinit_mutex( &driver->tx_mutex );
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driver->rx_size = 0;
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driver->tx_size = 0;
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driver->last_transmit_result = kNoErr;
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driver->last_receive_result = kNoErr;
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while (UART_GetLineStatus(driver->id, UART_LINESTATUS_TEMT)!= SET)
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;
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UART_Disable(driver->id);
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/* de-register interrupt callbacks */
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NVIC_DisableIRQ(UART_IRQn_BASE + driver->id);
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install_int_callback(UART_INT_BASE + driver->id, UART_INT_RDA, 0);
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return 0;
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}
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#else
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#define NUM_UART_PORTS 3
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#define UART_IRQn_BASE UART0_IRQn
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#define UART_INT_BASE INT_UART0
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static platform_uart_driver_t uart_drivers[NUM_UART_PORTS];
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static void (*uart_8bit_cb_p[NUM_UART_PORTS]) ();
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static void (*uart_9bit_cb_p[NUM_UART_PORTS]) ();
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#define SET_RX_BUF_SIZE(uart_data_p, size) \
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uart_data_p->rx_ringbuf.buf_size = size
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#define GET_RX_BUF_SIZE(uart_data_p) (uart_data_p->rx_ringbuf.buf_size)
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#define SET_DMA_BLK_SIZE(uart_data_p, size) \
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uart_data_p->rx_ringbuf.dma_block_size = size
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#define GET_DMA_BLK_SIZE(uart_data_p) (uart_data_p->rx_ringbuf.dma_block_size)
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#define DEFINE_UART_CB(id, mode) \
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static void \
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uart ## id ## _ ## mode ## bit_cb() {\
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uart_ ## mode ## bit_cb(id); }
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#define GET_UART_CB(id, mode) uart ## id ## _ ## mode ## bit_cb
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/* UART callback functions */
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static void uart_8bit_cb(int port_num)
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{
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uint8_t recv_byte;
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platform_uart_driver_t* driver = &uart_drivers[port_num];
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/* Receive new data */
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while (UART_GetLineStatus(port_num, UART_LINESTATUS_DR) == SET) {
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if (ring_buffer_is_full(driver->rx_ring_buffer) == 0) {
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recv_byte = UART_ReceiveData(port_num);
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ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
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if ( ( driver->rx_size > 0 ) &&
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( ring_buffer_used_space( driver->rx_ring_buffer) >= driver->rx_size ) ) {
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mico_rtos_set_semaphore( &driver->rx_complete );
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driver->rx_size = 0;
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}
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} else {
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/* Rx Buffer is full, discard received data */
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if (driver->flow_control != FLOW_CONTROL_DISABLED) {
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/* We need to mask the interrupt till the data
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is read; otherwise we keep getting
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data-ready interrupt infinitely */
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UART_IntMask(port_num, UART_INT_RDA, MASK);
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return;
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} else {
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UART_ReceiveData(port_num);
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}
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}
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}
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}
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static void uart_9bit_cb(int port_num)
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{
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uint16_t data;
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platform_uart_driver_t* driver = &uart_drivers[port_num];
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uint8_t recv_byte;
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/* Receive new data */
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while (UART_GetLineStatus(port_num, UART_LINESTATUS_DR) == SET) {
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if (ring_buffer_free_space(driver->rx_ring_buffer) > 1) {
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data = UART_Receive9bits(port_num);
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recv_byte = (uint8_t) ((data >> 8) & 0x01);
|
|
ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
|
|
recv_byte = (uint8_t) (data & 0xFF);
|
|
ring_buffer_write( driver->rx_ring_buffer, &recv_byte,1 );
|
|
|
|
if ( ( driver->rx_size > 0 ) &&
|
|
( ring_buffer_used_space( driver->rx_ring_buffer ) >= driver->rx_size ) ) {
|
|
mico_rtos_set_semaphore( &driver->rx_complete );
|
|
driver->rx_size = 0;
|
|
}
|
|
} else {
|
|
/* Rx Buffer is full, discard received data */
|
|
if (driver->flow_control != FLOW_CONTROL_DISABLED) {
|
|
/* We need to mask the interrupt till the data
|
|
is read; otherwise we keep getting
|
|
data-ready interrupt infinitely */
|
|
UART_IntMask(port_num, UART_INT_RDA, MASK);
|
|
return;
|
|
} else {
|
|
UART_Receive9bits(port_num);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
DEFINE_UART_CB(0, 8)
|
|
DEFINE_UART_CB(1, 8)
|
|
DEFINE_UART_CB(0, 9)
|
|
DEFINE_UART_CB(1, 9)
|
|
#if (NUM_UART_PORTS > 2)
|
|
DEFINE_UART_CB(2, 8)
|
|
DEFINE_UART_CB(2, 9)
|
|
#if (NUM_UART_PORTS > 3)
|
|
DEFINE_UART_CB(3, 8)
|
|
DEFINE_UART_CB(3, 9)
|
|
#endif
|
|
#endif
|
|
|
|
|
|
static void fill_cb_array()
|
|
{
|
|
uart_8bit_cb_p[0] = GET_UART_CB(0, 8);
|
|
uart_8bit_cb_p[1] = GET_UART_CB(1, 8);
|
|
uart_9bit_cb_p[0] = GET_UART_CB(0, 9);
|
|
uart_9bit_cb_p[1] = GET_UART_CB(1, 9);
|
|
#if (NUM_UART_PORTS > 2)
|
|
uart_8bit_cb_p[2] = GET_UART_CB(2, 8);
|
|
uart_9bit_cb_p[2] = GET_UART_CB(2, 9);
|
|
#if (NUM_UART_PORTS > 3)
|
|
uart_8bit_cb_p[3] = GET_UART_CB(3, 8);
|
|
uart_9bit_cb_p[3] = GET_UART_CB(3, 9);
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
|
|
int platform_uart_init(int port_id, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer)
|
|
{
|
|
UART_CFG_Type uartcfg;
|
|
UART_FifoCfg_Type fifocfg;
|
|
platform_uart_driver_t* driver;
|
|
int ret;
|
|
|
|
//sys_work_queue_init();
|
|
if (port_id < 0 || port_id >= NUM_UART_PORTS) {
|
|
UART_LOG("Port %d not enabled\r\n", port_id);
|
|
return -1;
|
|
}
|
|
fill_cb_array();
|
|
|
|
driver = &uart_drivers[port_id];
|
|
driver->id = port_id;
|
|
|
|
switch (driver->id) {
|
|
case UART0_ID:
|
|
CLK_SetUARTClkSrc(CLK_UART_ID_0, CLK_UART_FAST);
|
|
CLK_ModuleClkEnable(CLK_UART0);
|
|
break;
|
|
case UART1_ID:
|
|
CLK_SetUARTClkSrc(CLK_UART_ID_1, CLK_UART_SLOW);
|
|
CLK_ModuleClkEnable(CLK_UART1);
|
|
break;
|
|
case UART2_ID:
|
|
CLK_SetUARTClkSrc(CLK_UART_ID_2, CLK_UART_SLOW);
|
|
CLK_ModuleClkEnable(CLK_UART2);
|
|
break;
|
|
}
|
|
/* Initialize the UART port's mdev structure */
|
|
driver->rx_size = 0;
|
|
driver->tx_size = 0;
|
|
driver->last_transmit_result = kNoErr;
|
|
driver->last_receive_result = kNoErr;
|
|
|
|
uartcfg.baudRate = config->baud_rate;
|
|
uartcfg.stickyParity = DISABLE;
|
|
fifocfg.fifoEnable = ENABLE;
|
|
|
|
switch (config->data_width) {
|
|
case DATA_WIDTH_5BIT:
|
|
uartcfg.dataBits = UART_DATABITS_5;
|
|
break;
|
|
case DATA_WIDTH_6BIT:
|
|
uartcfg.dataBits = UART_DATABITS_6;
|
|
break;
|
|
case DATA_WIDTH_7BIT:
|
|
uartcfg.dataBits = UART_DATABITS_7;
|
|
break;
|
|
case DATA_WIDTH_8BIT:
|
|
uartcfg.dataBits = UART_DATABITS_8;
|
|
break;
|
|
case DATA_WIDTH_9BIT:
|
|
uartcfg.dataBits = UART_DATABITS_8;
|
|
uartcfg.parity = UART_PARITY_EVEN;
|
|
uartcfg.stickyParity = DISABLE;
|
|
fifocfg.fifoEnable = DISABLE;
|
|
break;
|
|
default:
|
|
uartcfg.dataBits = UART_DATABITS_8;
|
|
break;
|
|
}
|
|
switch ( config->parity )
|
|
{
|
|
case NO_PARITY:
|
|
uartcfg.parity = UART_PARITY_NONE;
|
|
break;
|
|
|
|
case EVEN_PARITY:
|
|
uartcfg.parity = UART_PARITY_EVEN;
|
|
break;
|
|
|
|
case ODD_PARITY:
|
|
uartcfg.parity = UART_PARITY_ODD;
|
|
break;
|
|
|
|
default:
|
|
uartcfg.parity = UART_PARITY_NONE;
|
|
break;
|
|
}
|
|
if (config->flow_control != FLOW_CONTROL_DISABLED) {
|
|
fifocfg.autoFlowControl = ENABLE;
|
|
} else {
|
|
fifocfg.autoFlowControl = DISABLE;
|
|
}
|
|
|
|
if ( config->stop_bits == STOP_BITS_1 )
|
|
UART_SetStopBits(port_id, UART_STOPBITS_1);
|
|
else
|
|
UART_SetStopBits(port_id, UART_STOPBITS_2);
|
|
|
|
fifocfg.rxFifoLevel = UART_RXFIFO_BYTE_1;
|
|
fifocfg.txFifoLevel = UART_TXFIFO_HALF_EMPTY;
|
|
fifocfg.peripheralBusType = UART_PERIPHERAL_BITS_8;
|
|
fifocfg.fifoDmaEnable = DISABLE;
|
|
|
|
UART_Disable(driver->id);
|
|
UART_Enable(driver->id);
|
|
UART_Init(driver->id, &uartcfg);
|
|
UART_FifoConfig(driver->id, &fifocfg);
|
|
|
|
/* initialize dma driver */
|
|
ret = dma_drv_init();
|
|
if (ret != WM_SUCCESS) {
|
|
UART_LOG("Failed to initialize dma driver\r\n");
|
|
return NULL;
|
|
}
|
|
ret = sys_work_queue_init();
|
|
if (ret != WM_SUCCESS) {
|
|
UART_LOG("Failed to initialize system workqueue\r\n");
|
|
return NULL;
|
|
}
|
|
if (optional_ring_buffer != NULL){
|
|
/* Note that the ring_buffer should've been initialised first */
|
|
driver->rx_ring_buffer = optional_ring_buffer;
|
|
|
|
} else {
|
|
uint8_t *pbuf;
|
|
pbuf = os_mem_alloc(512);
|
|
ring_buffer_init(driver->rx_ring_buffer, pbuf, 512);
|
|
}
|
|
driver->rx_size = 0;
|
|
|
|
/* Enable UART to send dma request to DMAC */
|
|
UART_DmaCmd(port_id, ENABLE);
|
|
uart_dma_read_start(port_id,
|
|
(uint8_t *)driver->rx_ring_buffer->buffer,
|
|
driver->rx_ring_buffer->size);
|
|
UART_IntMask(driver->id, UART_INT_RDA, UNMASK);
|
|
|
|
/* Configure the pinmux for uart pins */
|
|
board_uart_pin_config(driver->id);
|
|
|
|
|
|
return WM_SUCCESS;
|
|
}
|
|
|
|
uint32_t mico_get_time_no_os(void)
|
|
{
|
|
return os_total_ticks_get();
|
|
}
|
|
|
|
OSStatus platform_uart_receive_bytes( int port_id, uint8_t* data_in, uint32_t expected_data_size, uint32_t timeout_ms )
|
|
{
|
|
OSStatus err = kNoErr;
|
|
platform_uart_driver_t* driver;
|
|
|
|
if (port_id < 0 || port_id >= NUM_UART_PORTS) {
|
|
UART_LOG("Port %d not enabled\r\n", port_id);
|
|
return -1;
|
|
}
|
|
|
|
|
|
driver = &uart_drivers[port_id];
|
|
|
|
|
|
if (( data_in == NULL ) || ( expected_data_size == 0 )) {
|
|
err = kParamErr;
|
|
goto exit;
|
|
}
|
|
|
|
|
|
while (expected_data_size != 0)
|
|
{
|
|
uint32_t transfer_size = MIN( driver->rx_ring_buffer->size/2, expected_data_size );
|
|
|
|
/* Check if ring buffer already contains the required amount of data. */
|
|
if ( transfer_size > ring_buffer_used_space( driver->rx_ring_buffer ) )
|
|
{
|
|
/* Set rx_size and wait in rx_complete semaphore until data reaches rx_size or timeout occurs */
|
|
driver->rx_size = transfer_size;
|
|
|
|
if ( mico_rtos_get_semaphore( &driver->rx_complete, timeout_ms) != kNoErr )
|
|
{
|
|
driver->rx_size = 0;
|
|
return kTimeoutErr;
|
|
}
|
|
|
|
/* Reset rx_size to prevent semaphore being set while nothing waits for the data */
|
|
driver->rx_size = 0;
|
|
}
|
|
|
|
expected_data_size -= transfer_size;
|
|
|
|
// Grab data from the buffer
|
|
do
|
|
{
|
|
uint8_t* available_data;
|
|
uint32_t bytes_available;
|
|
|
|
ring_buffer_get_data( driver->rx_ring_buffer, &available_data, &bytes_available );
|
|
bytes_available = MIN( bytes_available, transfer_size );
|
|
memcpy( data_in, available_data, bytes_available );
|
|
transfer_size -= bytes_available;
|
|
data_in = ( (uint8_t*) data_in + bytes_available );
|
|
ring_buffer_consume( driver->rx_ring_buffer, bytes_available );
|
|
} while ( transfer_size != 0 );
|
|
}
|
|
|
|
if ( expected_data_size != 0 )
|
|
{
|
|
return kGeneralErr;
|
|
}
|
|
else
|
|
{
|
|
return kNoErr;
|
|
}
|
|
|
|
|
|
exit:
|
|
//platform_mcu_powersave_enable();
|
|
return err;
|
|
}
|
|
|
|
|
|
OSStatus platform_uart_transmit_bytes( int port_id, const uint8_t* data_out, uint32_t size )
|
|
{
|
|
int i;
|
|
|
|
if (port_id < 0 || port_id >= NUM_UART_PORTS) {
|
|
UART_LOG("Port %d not enabled\r\n", port_id);
|
|
return kGeneralErr;
|
|
}
|
|
|
|
for(i=0; i<size; i++) {
|
|
while (UART_GetLineStatus(port_id,
|
|
UART_LINESTATUS_TDRQ) != SET) {
|
|
os_thread_relinquish();
|
|
}
|
|
|
|
UART_SendData(port_id, data_out[i]);
|
|
}
|
|
return kNoErr;
|
|
}
|
|
|
|
|
|
|
|
OSStatus platform_uart_get_length_in_buffer( int port_id )
|
|
{
|
|
platform_uart_driver_t* driver;
|
|
|
|
if (port_id < 0 || port_id >= NUM_UART_PORTS) {
|
|
UART_LOG("Port %d not enabled\r\n", port_id);
|
|
return 0;
|
|
}
|
|
|
|
|
|
driver = &uart_drivers[port_id];
|
|
|
|
return ring_buffer_used_space( driver->rx_ring_buffer );
|
|
}
|
|
|
|
|
|
OSStatus platform_uart_deinit( int port_id )
|
|
{
|
|
platform_uart_driver_t* driver;
|
|
|
|
if (port_id < 0 || port_id >= NUM_UART_PORTS) {
|
|
UART_LOG("Port %d not enabled\r\n", port_id);
|
|
return 0;
|
|
}
|
|
|
|
|
|
driver = &uart_drivers[port_id];
|
|
|
|
mico_rtos_deinit_semaphore( &driver->rx_complete );
|
|
mico_rtos_deinit_semaphore( &driver->tx_complete );
|
|
mico_rtos_deinit_semaphore( &driver->sem_wakeup );
|
|
mico_rtos_deinit_mutex( &driver->tx_mutex );
|
|
driver->rx_size = 0;
|
|
driver->tx_size = 0;
|
|
driver->last_transmit_result = kNoErr;
|
|
driver->last_receive_result = kNoErr;
|
|
|
|
while (UART_GetLineStatus(port_id, UART_LINESTATUS_TEMT)!= SET)
|
|
;
|
|
|
|
UART_Disable(port_id);
|
|
|
|
/* de-register interrupt callbacks */
|
|
NVIC_DisableIRQ(UART_IRQn_BASE + port_id);
|
|
install_int_callback(UART_INT_BASE + port_id, UART_INT_RDA, 0);
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|