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252 lines
8.0 KiB
C
252 lines
8.0 KiB
C
/*
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* @brief LPC5410x I2C master driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Sets HIGH and LOW duty cycle registers */
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void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
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{
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/* Limit to usable range of timing values */
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if (sclH < 2) {
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sclH = 2;
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}
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else if (sclH > 9) {
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sclH = 9;
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}
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if (sclL < 2) {
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sclL = 2;
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}
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else if (sclL > 9) {
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sclL = 9;
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}
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pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07);
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}
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/* Set up bus speed for LPC_I2C interface */
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uint32_t Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
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{
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#if 0
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uint32_t scl;
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scl = Chip_Clock_GetAsyncSyscon_ClockRate() / (Chip_I2C_GetClockDiv(pI2C) * busSpeed);
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Chip_I2CM_SetDutyCycle(pI2C, (scl >> 1), (scl - (scl >> 1)));
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#endif
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// Wecan ToDo modify base on lpconen_2_14_1 ==> hw_i2cmd.c => i2cm_set_clock_rate 2015.06.04
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uint32_t scl;
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uint32_t inRate,div;
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inRate = Chip_Clock_GetAsyncSyscon_ClockRate();
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/* Determine the best I2C clock dividers to generate the target I2C master clock */
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/* The maximum SCL and SCH dividers are 7, for a maximum divider set of 14 */
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/* The I2C master divider is between 1 and 65536. */
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/* Pick a main I2C divider that allows centered SCL/SCH dividers */
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div = inRate / (busSpeed << 3);
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if (div == 0) {
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div = 1;
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}
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Chip_I2C_SetClockDiv(pI2C, div);
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/* Determine SCL/SCH dividers */
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scl = inRate / (div * busSpeed);
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Chip_I2CM_SetDutyCycle(pI2C, (scl >> 1), (scl - (scl >> 1)));
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return inRate / (div * scl);
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/////////////////////////////////////////////////////////////////////////////////////////////////////
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}
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/* Master transfer state change handler handler */
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uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
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{
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uint32_t status = Chip_I2CM_GetStatus(pI2C);
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if (status & I2C_STAT_MSTRARBLOSS) {
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/* Master Lost Arbitration */
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/* Set transfer status as Arbitration Lost */
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xfer->status = I2CM_STATUS_ARBLOST;
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/* Clear Status Flags */
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Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS);
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/* Master continue */
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if (status & I2C_STAT_MSTPENDING) {
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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}
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}
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else if (status & I2C_STAT_MSTSTSTPERR) {
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/* Master Start Stop Error */
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/* Set transfer status as Bus Error */
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xfer->status = I2CM_STATUS_BUS_ERROR;
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/* Clear Status Flags */
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Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTSTSTPERR);
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/* Master continue */
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if (status & I2C_STAT_MSTPENDING) {
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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}
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}
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else if (status & I2C_STAT_MSTPENDING) {
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/* Master is Pending */
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/* Branch based on Master State Code */
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switch (Chip_I2CM_GetMasterState(pI2C)) {
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case I2C_STAT_MSTCODE_IDLE: /* Master idle */
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/* Can transition to idle between transmit and receive states */
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if (xfer->txSz) {
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/* Start transmit state */
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Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1));
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTART;
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}
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else if (xfer->rxSz) {
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/* Start receive state with start ot repeat start */
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Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | 0x1);
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTART;
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}
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else {
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/* No data to send, done */
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xfer->status = I2CM_STATUS_OK;
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}
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break;
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case I2C_STAT_MSTCODE_RXREADY: /* Receive data is available */
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/* Read Data up until the buffer size */
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if (xfer->rxSz) {
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*xfer->rxBuff = pI2C->MSTDAT;
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xfer->rxBuff++;
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xfer->rxSz--;
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}
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if (xfer->rxSz) {
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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}
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else {
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/* Last byte to receive, send stop after byte received */
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE | I2C_MSTCTL_MSTSTOP;
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}
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break;
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case I2C_STAT_MSTCODE_TXREADY: /* Master Transmit available */
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if (xfer->txSz) {
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/* If Tx data available transmit data and continue */
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pI2C->MSTDAT = (uint32_t) *xfer->txBuff;
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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xfer->txBuff++;
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xfer->txSz--;
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}
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else if (xfer->rxSz == 0) {
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP;
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}
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else {
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/* Start receive state with start ot repeat start */
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Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | 0x1);
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTART;
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}
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break;
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case I2C_STAT_MSTCODE_NACKADR: /* Slave address was NACK'ed */
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/* Set transfer status as NACK on address */
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xfer->status = I2CM_STATUS_NAK_ADR;
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP;
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break;
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case I2C_STAT_MSTCODE_NACKDAT: /* Slave data was NACK'ed */
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/* Set transfer status as NACK on data */
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xfer->status = I2CM_STATUS_NAK_DAT;
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pI2C->MSTCTL = I2C_MSTCTL_MSTSTOP;
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break;
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default:
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/* Illegal I2C master state machine case. This should never happen.
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Try to advance state machine by continuing. */
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xfer->status = I2CM_STATUS_ERROR;
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pI2C->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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break;
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}
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}
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else {
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/* Unsupported operation. This may be a call to the master handler
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for a wrong interrupt type. This handler should only be called when a
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master arbitration loss, master start/stop error, or master pending status
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occurs. */
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xfer->status = I2CM_STATUS_ERROR;
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}
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return xfer->status != I2CM_STATUS_BUSY;
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}
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/* Transmit and Receive data in master mode */
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void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
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{
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/* set the transfer status as busy */
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xfer->status = I2CM_STATUS_BUSY;
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/* Reset master state machine */
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Chip_I2CM_Disable(pI2C);
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Chip_I2CM_Enable(pI2C);
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/* Clear controller state. */
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Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR);
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/* Handle transfer via initial call to handler */
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Chip_I2CM_XferHandler(pI2C, xfer);
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}
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/* Transmit and Receive data in master mode */
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uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
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{
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/* start transfer */
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Chip_I2CM_Xfer(pI2C, xfer);
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while (xfer->status == I2CM_STATUS_BUSY) {
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/* wait for status change interrupt */
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while (!Chip_I2CM_IsMasterPending(pI2C)) {}
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/* call state change handler */
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Chip_I2CM_XferHandler(pI2C, xfer);
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}
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return (xfer->status == I2CM_STATUS_OK);
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}
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