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https://github.com/oopuuu/zTC1.git
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265 lines
7.9 KiB
C
265 lines
7.9 KiB
C
/*
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* @brief LPC540XX SPI driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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STATIC void SPI_Send_Data_RxIgnore(LPC_SPI_T *pSPI,
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SPI_DATA_SETUP_T *pXfSetup)
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{
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if (pXfSetup->TxCnt == (pXfSetup->Length - 1)) {
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Chip_SPI_SendLastFrame_RxIgnore(pSPI, pXfSetup->pTx[pXfSetup->TxCnt], pXfSetup->DataSize);
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}
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else {
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Chip_SPI_SendMidFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt]);
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}
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pXfSetup->TxCnt++;
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}
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STATIC void SPI_Send_Data(LPC_SPI_T *pSPI,
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SPI_DATA_SETUP_T *pXfSetup)
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{
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if (pXfSetup->TxCnt == (pXfSetup->Length - 1)) {
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Chip_SPI_SendLastFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt], pXfSetup->DataSize);
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}
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else {
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Chip_SPI_SendMidFrame(pSPI, pXfSetup->pTx[pXfSetup->TxCnt]);
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}
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pXfSetup->TxCnt++;
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}
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STATIC void SPI_Send_Dummy(LPC_SPI_T *pSPI,
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SPI_DATA_SETUP_T *pXfSetup)
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{
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if (pXfSetup->RxCnt == (pXfSetup->Length - 1)) {
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Chip_SPI_SendLastFrame(pSPI, 0x55, pXfSetup->DataSize);
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}
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else {
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Chip_SPI_SendMidFrame(pSPI, 0x55);
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}
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}
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STATIC void SPI_Receive_Data(LPC_SPI_T *pSPI,
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SPI_DATA_SETUP_T *pXfSetup)
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{
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pXfSetup->pRx[pXfSetup->RxCnt] = Chip_SPI_ReceiveFrame(pSPI);
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pXfSetup->RxCnt++;
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Calculate the Clock Rate Divider for SPI Peripheral */
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uint32_t Chip_SPI_CalClkRateDivider(LPC_SPI_T *pSPI, uint32_t bitRate)
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{
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uint32_t SPIClk;
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uint32_t DivVal = 1;
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/* Get SPI clock rate */
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SPIClk = Chip_Clock_GetAsyncSysconClockRate(); /*The peripheral clock for both SPIs is the Async Syscon clock*/
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DivVal = SPIClk / bitRate;
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return DivVal;
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}
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/* Initialize the SPI */
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void Chip_SPI_IF_Init(LPC_SPI_T *pSPI, SPI_MODECONFIG_T *pConfig)
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{
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uint32_t EnStat;
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Chip_SPI_Init(pSPI);
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EnStat = pSPI->CFG & SPI_CFG_SPI_EN;
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/* Disable before update CFG register */
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if (EnStat) {
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Chip_SPI_Disable(pSPI);
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}
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/* SPI Configurate */
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pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) |
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((uint32_t) pConfig->SSELPol);
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if ( pConfig->Mode == SPI_CFG_MASTER_EN ) {
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/* Rate Divider setting */
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pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv);
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}
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/* Clear status flag*/
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Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD);
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/* Return the previous state */
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if (EnStat) {
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Chip_SPI_Enable(pSPI);
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}
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}
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/* Disable/Enable Interrupt */
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void Chip_SPI_Int_Cmd(LPC_SPI_T *pSPI, uint32_t IntMask, FunctionalState NewState)
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{
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if (NewState == ENABLE) {
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Chip_SPI_EnableInts(pSPI, IntMask);
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}
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else {
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Chip_SPI_DisableInts(pSPI, IntMask);
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}
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}
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/*Send and Receive SPI Data */
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uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
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{
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uint32_t Status;
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/* Clear status */
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Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD);
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Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF);
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pXfSetup->TxCnt = pXfSetup->RxCnt = 0;
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while ((pXfSetup->TxCnt < pXfSetup->Length) ||
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(pXfSetup->RxCnt < pXfSetup->Length)) {
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Status = Chip_SPI_GetStatus(pSPI);
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/* In case of TxReady */
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if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) {
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SPI_Send_Data(pSPI, pXfSetup);
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}
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/*In case of Rx ready */
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if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) {
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SPI_Receive_Data(pSPI, pXfSetup);
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}
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}
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/* Check error */
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if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR)) {
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return 0;
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}
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return pXfSetup->TxCnt;
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}
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uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
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{
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/* Clear status */
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Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD);
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Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF | SPI_TXCTL_RXIGNORE);
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pXfSetup->TxCnt = pXfSetup->RxCnt = 0;
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while (pXfSetup->TxCnt < pXfSetup->Length) {
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/* Wait for TxReady */
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while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {}
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SPI_Send_Data_RxIgnore(pSPI, pXfSetup);
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}
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/* Make sure the last frame sent completely*/
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while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD)) {}
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Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD);
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/* Check overrun error */
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if (Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXUR) {
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return 0;
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}
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return pXfSetup->TxCnt;
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}
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uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
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{
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/* Clear status */
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Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD);
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Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF);
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pXfSetup->TxCnt = pXfSetup->RxCnt = 0;
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while (pXfSetup->RxCnt < pXfSetup->Length) {
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/* Wait for TxReady */
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while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {}
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SPI_Send_Dummy(pSPI, pXfSetup);
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/* Wait for receive data */
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while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY)) {}
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SPI_Receive_Data(pSPI, pXfSetup);
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}
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/* Check overrun error */
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if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR)) {
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return 0;
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}
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return pXfSetup->RxCnt;
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}
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/* SPI Interrupt Read/Write with 8-bit frame width */
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Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
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{
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uint32_t Status;
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Status = Chip_SPI_GetStatus(pSPI);
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/* Check error in INTSTAT register */
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if (Status & (SPI_STAT_RXOV | SPI_STAT_TXUR)) {
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return ERROR;
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}
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if (pXfSetup->TxCnt == 0) {
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Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF);
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}
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if (pXfSetup->pRx == NULL) {
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if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) {
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SPI_Send_Data_RxIgnore(pSPI, pXfSetup);
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}
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}
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else {
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/* check if Tx ready */
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if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) {
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SPI_Send_Data(pSPI, pXfSetup);
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}
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/* check if RX FIFO contains data */
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if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) {
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SPI_Receive_Data(pSPI, pXfSetup);
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}
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}
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return SUCCESS;
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}
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// end file
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