mirror of
https://github.com/oopuuu/zTC1.git
synced 2025-12-15 14:38:13 +08:00
97 lines
3.2 KiB
Tcl
97 lines
3.2 KiB
Tcl
set MODE_STD 0
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set MODE_DUAL 1
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set MODE_QUAD 2
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set FLASH_BASE (0x00803000)
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set REG_FLASH_OPERATE_SW [expr $FLASH_BASE + 0 * 4]
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set ADDR_SW_REG_POSI (0)
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set ADDR_SW_REG_MASK (0xFFFFFF)
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set OP_TYPE_SW_POSI (24)
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set OP_TYPE_SW_MASK (0x1F)
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set OP_SW [expr 0x01 << 29]
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set WP_VALUE [expr 0x01 << 30]
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set BUSY_SW [expr 0x01 << 31]
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set REG_FLASH_DATA_SW_FLASH [expr $FLASH_BASE + 1 * 4]
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set REG_FLASH_DATA_FLASH_SW [expr $FLASH_BASE + 2 * 4]
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set REG_FLASH_RDID_DATA_FLASH [expr $FLASH_BASE + 4 * 4]
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set REG_FLASH_SR_DATA_CRC_CNT [expr $FLASH_BASE + 5 * 4]
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set SR_DATA_FLASH_POSI (0)
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set SR_DATA_FLASH_MASK (0xFF)
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set CRC_ERROR_COUNT_POSI (8)
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set CRC_ERROR_COUNT_MASK (0xFF)
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set DATA_FLASH_SW_SEL_POSI (16)
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set DATA_FLASH_SW_SEL_MASK (0x07)
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set DATA_SW_FLASH_SEL_POSI (19)
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set DATA_SW_FLASH_SEL_MASK (0x07)
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set REG_FLASH_CONF [expr $FLASH_BASE + 7 * 4]
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set FLASH_CLK_CONF_POSI (0)
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set FLASH_CLK_CONF_MASK (0x0F)
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set MODEL_SEL_POSI (4)
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set MODEL_SEL_MASK (0x1F)
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set FWREN_FLASH_CPU [expr 0x01 << 9]
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set WRSR_DATA_POSI (10)
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set WRSR_DATA_MASK (0xFFFF)
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set CRC_EN [expr 0x01 << 26]
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set FLASH_OPCODE_WREN 1
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set FLASH_OPCODE_WRDI 2
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set FLASH_OPCODE_RDSR 3
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set FLASH_OPCODE_WRSR 4
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set FLASH_OPCODE_READ 5
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set FLASH_OPCODE_RDSR2 6
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set FLASH_OPCODE_WRSR2 7
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set FLASH_OPCODE_PP 12
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set FLASH_OPCODE_SE 13
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set FLASH_OPCODE_BE1 14
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set FLASH_OPCODE_BE2 15
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set FLASH_OPCODE_CE 16
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set FLASH_OPCODE_DP 17
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set FLASH_OPCODE_RFDP 18
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set FLASH_OPCODE_RDID 20
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set FLASH_OPCODE_HPM 1
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set FLASH_OPCODE_CRMR 22
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set FLASH_OPCODE_CRMR2 23
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proc read_reg { addr } {
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mem2array memar 32 $addr 1
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return $memar(0)
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}
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proc write_reg { addr val } {
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set memar(0) $val
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array2mem memar 32 $addr 1
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}
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proc flash_init { } {
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while { [expr [read_reg $::REG_FLASH_OPERATE_SW] & $::BUSY_SW] } { }
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write_reg $::REG_FLASH_CONF 0x00000215
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}
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proc flash_erase_sector { addr } {
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while { [expr [read_reg $::REG_FLASH_OPERATE_SW] & $::BUSY_SW] } { }
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set value [read_reg $::REG_FLASH_OPERATE_SW]
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set value [expr (($addr << $::ADDR_SW_REG_POSI)| ($::FLASH_OPCODE_SE << $::OP_TYPE_SW_POSI)| $::OP_SW | ($value & $::WP_VALUE))]
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write_reg $::REG_FLASH_OPERATE_SW $value
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while { [expr [read_reg $::REG_FLASH_OPERATE_SW] & $::BUSY_SW] } { }
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}
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proc flash_erase { addr size } {
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if { [expr $addr % 0x1000] || [expr $size % 0x1000] } {
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error "erase address $addr or size $size not aligned to 4K bytes"
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} else {
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while { $size } {
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flash_erase_sector $addr
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set addr [expr $addr + 0x1000]
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set size [expr $size - 0x1000]
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}
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}
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}
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