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151 lines
6.4 KiB
C
151 lines
6.4 KiB
C
/**
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******************************************************************************
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* @file platform_config.h
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provides common configuration for current platform.
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******************************************************************************
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*
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* The MIT License
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* Copyright (c) 2014 MXCHIP Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
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* IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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******************************************************************************
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/******************************************************
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* Macros
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******************************************************/
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/******************************************************
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* Constants
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******************************************************/
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#define HARDWARE_REVISION "1.0"
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#define DEFAULT_NAME "NUCLEO"
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#define MODEL "NUCLEO-F412ZG"
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/* MICO RTOS tick rate in Hz */
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#define MICO_DEFAULT_TICK_RATE_HZ (1000) //RTOS閺冨爼妫块悧锟<E682A7> 1ms
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/************************************************************************
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* Uncomment to disable watchdog. For debugging only */
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//#define MICO_DISABLE_WATCHDOG
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/************************************************************************
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* Uncomment to disable standard IO, i.e. printf(), etc. */
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//#define MICO_DISABLE_STDIO
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/************************************************************************
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* Enable press space go to boot */
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#define MICO_ENABLE_STDIO_TO_BOOT
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/************************************************************************
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* Uncomment to disable MCU powersave API functions */
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//#define MICO_DISABLE_MCU_POWERSAVE
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/************************************************************************
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* Uncomment to enable MCU real time clock */
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#define MICO_ENABLE_MCU_RTC
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/************************************************************************
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* Restore default and start easylink after press down EasyLink button for 3 seconds. */
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#define RestoreDefault_TimeOut (3000)
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/************************************************************************
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* CPU clock 100MHZ*/
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#define MCU_CLOCK_HZ (100000000)
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/************************************************************************
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* How many bits are used in NVIC priority configuration */
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#define CORTEX_NVIC_PRIO_BITS (4)
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/************************************************************************
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* Enable write protection to write-disabled embedded flash sectors */
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//#define MCU_EBANLE_FLASH_PROTECT
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#define HSE_SOURCE RCC_HSE_OFF /* Use internal crystal */
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#define AHB_CLOCK_DIVIDER RCC_SYSCLK_Div1 /* AHB clock = System clock */
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#define APB1_CLOCK_DIVIDER RCC_HCLK_Div2 /* APB1 clock = AHB clock / 2 */
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#define APB2_CLOCK_DIVIDER RCC_HCLK_Div1 /* APB2 clock = AHB clock / 1 */
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#define PLL_SOURCE RCC_PLLSource_HSI /* PLL source = external crystal */
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#define PLL_M_CONSTANT 16 /* PLLM = 16 */
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#define PLL_N_CONSTANT 400 /* PLLN = 400 */
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#define PLL_P_CONSTANT 4 /* PLLP = 4 */
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#define PPL_Q_CONSTANT 7 /* PLLQ = 7 */
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#define PPL_R_CONSTANT 2 /* PLLR = 2 */
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#define SYSTEM_CLOCK_SOURCE RCC_SYSCLKSource_PLLCLK /* System clock source = PLL clock */
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#define SYSTICK_CLOCK_SOURCE SysTick_CLKSource_HCLK /* SysTick clock source = AHB clock */
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#define INT_FLASH_WAIT_STATE FLASH_Latency_3 /* Internal flash wait state = 3 cycles */
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#define PWR_WakeUp_Pin PWR_WakeUp_Pin2 /* PWR_Wake_Up_Pin */
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/******************************************************
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* EMW1062 Options
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******************************************************/
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/* Wi-Fi chip module */
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#define EMW1062
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/* WiFi driver use gSPI mode, and share spi bus with other devices by different /cs pins */
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#define MICO_WIFI_SHARE_SPI_BUS
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/* GPIO pins are used to bootstrap Wi-Fi to SDIO or gSPI mode */
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//#define MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP
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/* Wi-Fi GPIO0 pin is used for out-of-band interrupt */
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#define MICO_WIFI_OOB_IRQ_GPIO_PIN ( 0 )
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/* Wi-Fi power pin is present */
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//#define MICO_USE_WIFI_POWER_PIN
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/* Wi-Fi reset pin is present */
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#define MICO_USE_WIFI_RESET_PIN
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/* Wi-Fi 32K pin is present */
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#define MICO_USE_WIFI_32K_PIN //WiFi濡<E6BFA1>虫健閺冨爼鎸撻悽鍗烆樆闁劍褰佹笟锟<E7AC9F>
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/* USE SDIO 1bit mode. */
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//#define SDIO_1_BIT
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/* Wi-Fi power pin is active high */
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//#define MICO_USE_WIFI_POWER_PIN_ACTIVE_HIGH
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/* WLAN Powersave Clock Source
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* The WLAN sleep clock can be driven from one of two sources:
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* 1. MCO (MCU Clock Output) - default
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* 2. WLAN 32K internal oscillator (30% inaccuracy)
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*/
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//#define MICO_USE_WIFI_32K_CLOCK_MCO
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//#define MICO_USE_BUILTIN_RF_DRIVER //鐞涖劎銇氶悽銊ュ敶闁劍鏆熼幑顕嗙礉閼板奔绗夐弰顖氼樆闁劎娈慠F driver
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#ifdef __cplusplus
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} /*extern "C" */
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#endif
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