mirror of
https://github.com/oopuuu/zTC1.git
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388 lines
10 KiB
C
388 lines
10 KiB
C
/**
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******************************************************************************
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* @file MicoDriverGpio.c
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* @author Magicoe.Niu
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* @version V0.0.1
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* @date 05-May-2015
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* @brief This file provide GPIO driver functions.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "mico_platform.h"
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#include "mico_rtos.h"
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#include "platform.h"
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#include "platform_peripheral.h"
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#include "chip.h"
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#include "power_control.h"
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#include "platform_logging.h"
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/******************************************************
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* Constants
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******************************************************/
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/******************************************************
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* Enumerations
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******************************************************/
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/******************************************************
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* Type Definitions
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******************************************************/
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/******************************************************
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* Structures
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******************************************************/
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/******************************************************
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* Variables Definitions
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******************************************************/
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/******************************************************
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* Function Declarations
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******************************************************/
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/******************************************************
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* Function Definitions
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******************************************************/
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OSStatus platform_gpio_init( const platform_gpio_t* gpio, platform_pin_config_t config )
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{
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uint32_t gpio_cfg_value;
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OSStatus err = kNoErr;
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uint32_t port, pin;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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port = gpio->port , pin = gpio->pin_number;
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// GPIO are always func0, need digital enabled, and defaults to no need input filter
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gpio_cfg_value = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
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if (config == INPUT_PULL_UP || config == OUTPUT_OPEN_DRAIN_PULL_UP)
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gpio_cfg_value |= IOCON_MODE_PULLUP;
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else if (config == INPUT_PULL_DOWN )
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gpio_cfg_value |= IOCON_MODE_PULLDOWN;
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else if (config == INPUT_HIGH_IMPEDANCE || config == OUTPUT_PUSH_PULL)
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gpio_cfg_value |= IOCON_MODE_INACT;
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if (port == 0 && (pin >=23 && pin <= 28)) {
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// I2C pins
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gpio_cfg_value |= IOCON_GPIO_MODE;
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} else {
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// non-I2C pins, process open drain settings.
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if (config == OUTPUT_OPEN_DRAIN_NO_PULL || config == OUTPUT_OPEN_DRAIN_PULL_UP)
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gpio_cfg_value |= IOCON_OPENDRAIN_EN;
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}
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Chip_IOCON_PinMuxSet(LPC_IOCON, port, pin, gpio_cfg_value);
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if (config == INPUT_PULL_UP || config == INPUT_PULL_DOWN || config == INPUT_HIGH_IMPEDANCE)
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Chip_GPIO_SetPinDIRInput(LPC_GPIO, port, pin);
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else
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Chip_GPIO_SetPinDIROutput(LPC_GPIO, port, pin);
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_deinit( const platform_gpio_t* gpio )
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{
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return platform_gpio_init(gpio, INPUT_HIGH_IMPEDANCE);
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}
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OSStatus platform_gpio_output_high( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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Chip_GPIO_SetPinState(LPC_GPIO, gpio->port, gpio->pin_number, 1); // Magicoe gpio->port->BSRRL = (uint16_t) ( 1 << gpio->pin_number );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_output_low( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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platform_mcu_powersave_disable();
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Chip_GPIO_SetPinState(LPC_GPIO, gpio->port, gpio->pin_number, 0); // Magicoe gpio->port->BSRRH = (uint16_t) ( 1 << gpio->pin_number );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_output_trigger( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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Chip_GPIO_SetPinToggle(LPC_GPIO, gpio->port, gpio->pin_number); // Magicoe gpio->port->ODR ^= (uint16_t) ( 1 << gpio->pin_number );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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bool platform_gpio_input_get( const platform_gpio_t* gpio )
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{
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bool result = false;
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platform_mcu_powersave_disable();
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require_quiet( gpio != NULL, exit);
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result = Chip_GPIO_GetPinState(LPC_GPIO, gpio->port, gpio->pin_number);
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exit:
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platform_mcu_powersave_enable();
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return result;
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}
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const IRQn_Type s_nvicIrqNdxTab[] =
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{
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PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn,
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PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn,
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};
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#define PININT_SLOT_CNT 8
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typedef struct _DS_PinIntAlloc
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{
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uint8_t inUses[PININT_SLOT_CNT];
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uint8_t portPins[PININT_SLOT_CNT];
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platform_gpio_irq_callback_t pfnCBs[PININT_SLOT_CNT];
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void *pArgs[PININT_SLOT_CNT];
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}DS_PinIntAlloc;
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static DS_PinIntAlloc s_irqAlc;
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OSStatus platform_gpio_irq_enable( const platform_gpio_t* gpio, platform_gpio_irq_trigger_t trigger, platform_gpio_irq_callback_t handler, void* arg )
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{
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OSStatus err = kNoErr;
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LPC_PIN_INT_T *pInt = LPC_PININT;
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platform_mcu_powersave_disable();
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uint32_t i, bv;
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IRQn_Type irqNdx;
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uint32_t portPins;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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portPins = (gpio->port << 5) + gpio->pin_number;
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// check if already registered
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for (i=0; i<PININT_SLOT_CNT; i++) {
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if (s_irqAlc.inUses[i])
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{
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if (s_irqAlc.portPins[i] == portPins)
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break;
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}
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}
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//require_action_quiet(i == PININT_SLOT_CNT, exit, err = kAlreadyInitializedErr);
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disable_interrupts();
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if(i == PININT_SLOT_CNT)
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{
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// find a free slot
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for (i=0; i<PININT_SLOT_CNT; i++) {
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if (!s_irqAlc.inUses[i])
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break;
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}
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}
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require_action_quiet(i < PININT_SLOT_CNT, exit, err = kNoResourcesErr);
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// use this slot
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bv = 1UL << i;
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irqNdx = s_nvicIrqNdxTab[i];
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NVIC_DisableIRQ(irqNdx);
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s_irqAlc.inUses[i] = 1;
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s_irqAlc.pfnCBs[i] = handler;
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s_irqAlc.pArgs[i] = arg;
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s_irqAlc.portPins[i] = (uint8_t) portPins;
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g_pInMux->PINTSEL[i] = portPins;
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pInt->IST = bv; // clear IRQ status for PININT slot i
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pInt->ISEL &= ~(bv); // set edge trigger
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if (trigger == IRQ_TRIGGER_RISING_EDGE)
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pInt->SIENR = bv;
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else if (trigger == IRQ_TRIGGER_FALLING_EDGE)
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pInt->SIENF = bv;
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else if (trigger == IRQ_TRIGGER_BOTH_EDGES)
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pInt->SIENR = bv , pInt->SIENF = bv;
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NVIC_EnableIRQ(irqNdx);
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exit:
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platform_mcu_powersave_enable();
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enable_interrupts();
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return err;
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}
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OSStatus platform_gpio_irq_disable( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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uint32_t i, portPin;
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IRQn_Type irqNdx;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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disable_interrupts();
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// Check if this gpio is mapped
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portPin = (gpio->port << 5) + gpio->pin_number;
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for (i=0; i<PININT_SLOT_CNT; i++) {
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if (s_irqAlc.portPins[i] == portPin)
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break;
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}
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require_action_quiet(i < PININT_SLOT_CNT, exit, err = kParamErr);
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irqNdx = s_nvicIrqNdxTab[i];
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if (s_irqAlc.inUses[i])
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{
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s_irqAlc.inUses[i] = 0;
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}
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NVIC_DisableIRQ(irqNdx);
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exit:
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platform_mcu_powersave_enable();
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enable_interrupts();
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return err;
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}
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/******************************************************
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* LPC54100 Internal Function Definitions
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******************************************************/
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OSStatus platform_gpio_irq_manager_init( void )
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{
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Chip_PININT_Init(LPC_PININT);
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memset(&s_irqAlc, 0, sizeof(s_irqAlc));
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return kNoErr;
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}
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OSStatus platform_gpio_enable_clock( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_IOCON);
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if(gpio->port == 0) {
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Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0);
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}
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if(gpio->port == 1) {
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Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1);
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}
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exit:
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return err;
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}
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//
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//OSStatus platform_gpio_set_alternate_function( platform_gpio_port_t* gpio_port, uint8_t pin_number, platform_pin_config_t output_type, GPIOPuPd_TypeDef pull_up_down_type, uint8_t alternation_function )
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//{
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// GPIO_InitTypeDef gpio_init_structure;
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// uint8_t port_number = platform_gpio_get_port_number( gpio_port );
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//
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// // platform_mcu_powersave_disable();
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//
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// if(gpio->port == 0) {
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// Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0);
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// }
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// if(gpio->port == 1) {
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// Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1);
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// }
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//
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//
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//
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// gpio_init_structure.GPIO_Speed = GPIO_Speed_50MHz;
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// gpio_init_structure.GPIO_Mode = GPIO_Mode_AF;
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// gpio_init_structure.GPIO_OType = output_type;
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// gpio_init_structure.GPIO_PuPd = pull_up_down_type;
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// gpio_init_structure.GPIO_Pin = (uint32_t) ( 1 << pin_number );
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//
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// GPIO_Init( gpio_port, &gpio_init_structure );
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// GPIO_PinAFConfig( gpio_port, pin_number, alternation_function );
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//
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// // platform_mcu_powersave_enable();
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//
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// return kNoErr;
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//}
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/******************************************************
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* IRQ Handler Definitions
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******************************************************/
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void _prvPinIntHandler(uint32_t slotNdx)
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{
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LPC_PIN_INT_T *pInt = LPC_PININT;
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pInt->IST = 1UL << slotNdx; // clear IRQ flag
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// call call-back handler
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if (s_irqAlc.inUses[slotNdx]) {
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if (s_irqAlc.pfnCBs[slotNdx]) {
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s_irqAlc.pfnCBs[slotNdx](s_irqAlc.pArgs[slotNdx]);
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}
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}
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}
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/******************************************************
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* IRQ Handler Mapping
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******************************************************/
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MICO_RTOS_DEFINE_ISR( PIN_INT0_IRQHandler )
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{
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_prvPinIntHandler(0);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT1_IRQHandler )
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{
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_prvPinIntHandler(1);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT2_IRQHandler )
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{
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_prvPinIntHandler(2);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT3_IRQHandler )
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{
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_prvPinIntHandler(3);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT4_IRQHandler )
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{
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_prvPinIntHandler(4);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT5_IRQHandler )
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{
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_prvPinIntHandler(5);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT6_IRQHandler )
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{
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_prvPinIntHandler(6);
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}
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MICO_RTOS_DEFINE_ISR( PIN_INT7_IRQHandler )
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{
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_prvPinIntHandler(7);
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}
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// end file --- MG.Niu ---
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