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173 lines
8.9 KiB
C
173 lines
8.9 KiB
C
/*
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* @brief Basic CMSIS include file for LPC5410x M4 core
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_5410X_H_
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#define __CMSIS_5410X_H_
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#include "lpc_types.h"
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#include "sys_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_5410X_M4 CHIP: LPC5410X M4 core CMSIS include file
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* @ingroup CHIP_5410X_CMSIS_DRIVERS
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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// Kill warning "#pragma push with no matching #pragma pop"
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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// #pragma push // FIXME not usable for IAR
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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#if !defined(CORE_M4)
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#error "CORE_M4 is not defined"
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#endif
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/** @defgroup CMSIS_5410X_M4_IRQ CHIP_5410X: LPC5410X M4 core peripheral interrupt numbers
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* @{
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*/
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typedef enum {
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/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
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Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
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BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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/****** LPC5410X Specific Interrupt Numbers ********************************************************/
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WDT_IRQn = 0, /*!< WWDT */
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BOD_IRQn = 1, /*!< BOD */
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Reserved2_IRQn = 2, /*!< Reserved Interrupt */
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DMA_IRQn = 3, /*!< DMA */
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GINT0_IRQn = 4, /*!< GINT0 */
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PIN_INT0_IRQn = 5, /*!< PININT0 */
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PIN_INT1_IRQn = 6, /*!< PININT1 */
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PIN_INT2_IRQn = 7, /*!< PININT2 */
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PIN_INT3_IRQn = 8, /*!< PININT3 */
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UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */
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MRT_IRQn = 10, /*!< Multi-rate timer interrupt */
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CT32B0_IRQn = 11, /*!< CTMR0 */
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CT32B1_IRQn = 12, /*!< CTMR1 */
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CT32B2_IRQn = 13, /*!< CTMR2 */
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CT32B3_IRQn = 14, /*!< CTMR3 */
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CT32B4_IRQn = 15, /*!< CTMR4 */
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SCT0_IRQn = 16, /*!< SCT */
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UART0_IRQn = 17, /*!< UART0 */
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UART1_IRQn = 18, /*!< UART1 */
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UART2_IRQn = 19, /*!< UART2 */
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UART3_IRQn = 20, /*!< UART3 */
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I2C0_IRQn = 21, /*!< I2C0 */
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I2C1_IRQn = 22, /*!< I2C1 */
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I2C2_IRQn = 23, /*!< I2C2 */
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SPI0_IRQn = 24, /*!< SPI0 */
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SPI1_IRQn = 25, /*!< SPI1 */
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ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */
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ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */
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ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */
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RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */
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Reserved30_IRQn = 30, /*!< Reserved Interrupt */
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MAILBOX_IRQn = 31, /*!< Mailbox */
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GINT1_IRQn = 32, /*!< GINT1 */
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PIN_INT4_IRQn = 33, /*!< External Interrupt 4 */
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PIN_INT5_IRQn = 34, /*!< External Interrupt 5 */
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PIN_INT6_IRQn = 35, /*!< External Interrupt 6 */
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PIN_INT7_IRQn = 36, /*!< External Interrupt 7 */
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Reserved37_IRQn = 37, /*!< Reserved Interrupt */
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Reserved38_IRQn = 38, /*!< Reserved Interrupt */
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Reserved39_IRQn = 39, /*!< Reserved Interrupt */
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RIT_IRQn = 40, /*!< Repetitive Interrupt Timer */
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Reserved41_IRQn = 41, /*!< Reserved Interrupt */
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Reserved42_IRQn = 42, /*!< Reserved Interrupt */
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Reserved43_IRQn = 43, /*!< Reserved Interrupt */
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Reserved44_IRQn = 44, /*!< Reserved Interrupt */
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} LPC5410X_IRQn_Type;
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/**
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* @}
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*/
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/** @defgroup CMSIS_5410X_M4_COMMON CHIP: LPC5410X M4 core Cortex CMSIS definitions
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* @{
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*/
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/* Configuration of the Cortex-M4 Processor and Core Peripherals */
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#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMSIS_5410X_H_ */
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