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65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/**
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*****************************************************************************
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* @file pmem.c
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* @author Ingrid
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* @version V1.0.0
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* @date 03-June-2013
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* @brief PMEM module driver interface
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*****************************************************************************
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* @attention
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*
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* This module support clk driver, all the other module need to consider how to
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* use these function
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*
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* <h2><center>© COPYRIGHT 2013 MVSilicon </center></h2>
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*/
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#ifndef __PMEM_H__
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#define __PMEM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif//__cplusplus
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/**<PATH SEL*/
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#define PMEM_ADC_MIX_PATH (1 << 0) /**<adc and phub module switch*/
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#define PMEM_SPI_PATH (1 << 2) /**<SPIS module switch*/
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#define PMEM_UART_PATH (1 << 3) /**<buart module switch*/
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#define PMEM_I2S_PATH (1 << 4) /**<I2S module switch*/
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/**<ERR CODE DEFINE*/
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#define PMEM_SPIS_BUART_ERR (-1) /**<spis and buart can't work in the same time*/
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/**<PMEM SPACE allocation*/
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#define PMEM_OFIFO_START_ADDR (0x0000) /**<start address of PMEM for output fifo */
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#define PMEM_OFIFO_MAX_LENGTH (0x8000) /**<depth of PMEM for output fifo */
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#define DEF_PCM_FIFO_LENGTH (0x3000) /**<depth of PMEM for output fifo */
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#define BT_FIFO_MAX_LENGTH (0x1C00) /**<depth of PMEM for output fifo */
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/**
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* @brief there are five master can write data into pmem, ADC,phub,SPIS,UART,I2S
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* but adc and phub, spis and buart can't work in the same time
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* @param Mode master read/write pmem path sel
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* @return err code
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* @arg PMEM_SPIS_BUART_ERR spis and buart set at the same time
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* >0 is current val in reg
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*/
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uint32_t PmemDataPathSel(uint8_t Mode);
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/**
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* @brief close the path for each master r/w pmem
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* @param Mode master read/write pmem path sel
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* @return NONE
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*/
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void PmemDataPathClose(uint8_t Mode);
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#ifdef __cplusplus
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}
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#endif//__cplusplus
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#endif
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