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312 lines
9.2 KiB
C
312 lines
9.2 KiB
C
/**
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*****************************************************************************
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* @file clk.h
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* @author lujiangang
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* @version V1.0.0
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* @date 29-May-2013
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* @brief clk module driver interface
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*****************************************************************************
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* @attention
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*
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* This module provide clk driver, all the other module need to consider how to
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* use these function
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*
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* <h2><center>© COPYRIGHT 2013 MVSilicon </center></h2>
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*/
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#ifndef __CLK_H__
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#define __CLK_H__
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#ifdef __cplusplus
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extern "C" {
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#endif//__cplusplus
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#define USB_MODE 1 /**<usb mode always 12M */
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#define NORMAL_MODE 0 /**<normal mode provide 12.288m and 11.2896M */
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#define MCLK_SRC_DPLL_12MHZ 0 /**<generally is usb mode */
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#define MCLK_SRC_EXTCLK 1 /**<extern clk input */
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#define MCLK_SRC_DPLL_12M288 2 /**<generate 12.288M */
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#define MCLK_SRC_DPLL_11M2896 3 /**<generate 11.2896M */
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/**
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* CLK module switch macro define
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*/
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typedef enum _CLK_MODULE_SWITCH
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{
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BUART_CLK_EN = (1 << 0), /**<buart module clk switch */
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FUART_CLK_EN = (1 << 1), /**<fuart module clk switch */
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DLUT_CLK_EN = (1 << 2), /**<DLUT module clk switch */
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DMAC_CLK_EN = (1 << 3), /**<DMAC module clk switch */
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IIS_CLK_EN = (1 << 4), /**<IIS module clk switch */
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LCDC_CLK_EN = (1 << 5), /**<LCDC module clk switch */
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PHUB_CLK_EN = (1 << 6), /**<PHUB module clk switch */
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SD_CLK_EN = (1 << 7), /**<SD module clk switch */
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SPIM_CLK_EN = (1 << 8), /**<SPIM module clk switch */
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SPIS_CLK_EN = (1 << 9), /**<SPIS module clk switch */
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TIMER0_CLK_EN = (1 << 10), /**<TIMER0 module clk switch */
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TIMER1_CLK_EN = (1 << 11), /**<TIMER1 module clk switch */
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DECODER_CLK_EN = (1 << 12), /**<DECODER module clk switch */
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SDRAM_CLK_EN = (1 << 13), /**<SDRAM module clk switch */
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FSHC_CLK_EN = (1 << 14), /**<FSHC module clk switch */
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USB_CLK_EN = (1 << 15), /**<USB module clk switch */
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CODEC_CLK_EN = (1 << 16), /**<CODEC module clk switch */
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ALL_MODULE_CLK_SWITCH = (0x1FFFF), /**<all module clk SWITCH*/
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} CLK_MODULE_SWITCH;
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/**
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* CLK module GATE switch macro define
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*/
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typedef enum _CLK_MODULE_GATE_SWITCH
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{
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CACHE_CLK_GATE_EN = (1 << 0), /**<CACHE module clk gating switch */
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CM3_CLK_GATE_EN = (1 << 1), /**<CM3 module clk gating switch */
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CODEC_CLK_GATE_EN = (1 << 2), /**<CODEC module clk gating switch */
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DMAC_CLK_GATE_EN = (1 << 3), /**<DMAC module clk gating switch */
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SDRAM_CLK_GATE_EN = (1 << 4), /**<SDRAM module clk gating switch */
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FSHC_CLK_GATE_EN = (1 << 5), /**<FSHC module clk gating switch */
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LCDC_CLK_GATE_EN = (1 << 6), /**<LCDC module clk gating switch */
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PMEM_CLK_GATE_EN = (1 << 7), /**<PMEM module clk gating switch */
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ROM_CLK_GATE_EN = (1 << 8), /**<ROM module clk gating switch */
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XMEM_CLK_GATE_EN = (1 << 9), /**<XMEM module clk gating switch */
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VMEM_CLK_GATE_EN = (1 << 10), /**<VMEM module clk gating switch */
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GPIO_CLK_GATE_EN = (1 << 11), /**<GPIO module clk gating switch */
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DLUT_CLK_GATE_EN = (1 << 12), /**<DLUT module clk gating switch */
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DEC_TX_CLK_GATE_EN = (1 << 13), /**<DEC TX module clk gating switch */
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DEC_REG_CLK_GATE_EN = (1 << 14), /**<DEC REG module clk gating switch */
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DEC_MP3_CLK_GATE_EN = (1 << 15), /**<DEC MP3 module clk gating switch */
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DEC_WMA_CLK_GATE_EN = (1 << 16), /**<DEC WMA module clk gating switch */
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DEC_SBC_CLK_GATE_EN = (1 << 17), /**<DEC SBC module clk gating switch */
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ALL_MODULE_CLK_GATE_SWITCH = (0x3FFFF), /**<all module clk gating SWITCH*/
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} CLK_MODULE_GATE_SWITCH;
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/**
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* @brief select flash module clk
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* @param ClkSel 0:pll_clk_60m
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* 1:sys_clk_96m sel this clk will affect by sys clk div
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* 2:pll_clk_80m
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* 3:pll_clk_48m
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* @return NONE
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*/
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void ClkFshcClkSel(uint32_t ClkSel);
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/**
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* @brief open module clk
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* @param ClkSel each module usb one bit control.
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* totally 16bits, can use enum type 'CLK_MODULE_SWITCH' to sel
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* which module clk need to open
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* @return NONE
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*/
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void ClkModuleEn(CLK_MODULE_SWITCH ClkSel);
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/**
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* @brief close module clk
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* @param ClkSel:each module usb one bit control.
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* totally 16bits, can use enum type 'CLK_MODULE_SWITCH' to sel which module clk need to close
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* @return NONE
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*/
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void ClkModuleDis(CLK_MODULE_SWITCH ClkSel);
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/**
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* @brief clk gate enable
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* @param ClkGateSel 0~17 bits are valid, can use enum type 'CLK_MODULE_GATE_SWITCH'
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* to sel which module clk need to open
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* @return NONE
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*/
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void ClkModuleGateEn(CLK_MODULE_GATE_SWITCH ClkGateSel);
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/**
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* @brief clk gate disable
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* @param ClkGateSel 0~17 bits are valid, can use enum type 'CLK_MODULE_GATE_SWITCH'
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* to sel which module clk need to close
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* @return NONE
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*/
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void ClkModuleGateDis(CLK_MODULE_GATE_SWITCH ClkGateSel);
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/**
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* @brief mclk sel
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* @param Mode:
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* 0 sys clk 12M
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* 1 extern mclk input
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* 2 clk 12.288M
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* 3 clk 11.2896M
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* @return NONE
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*/
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void ClkMclkSel(uint8_t Mode);
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/**
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* @brief clk switch from rc48m to dpll
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* sysclk is 96m, but fshc clk is 80m, doesn't affect by sys clk div
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* @param ClkSrc 0:32.768K, 1~31:1M~31M
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* @return TRUE OR FALSE
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*/
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bool ClkPorRcToDpll(uint8_t ClkSrc);
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/**
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* @brief enable DPLL CLK GATING
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* @param ClkGatEn 1:enable 0:disable
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* @return NONE
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*/
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void ClkDpllClkGatingEn(bool ClkGatEn);
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/**
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* @brief disable dpll auto calibration
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* @param DefaultNdac must a average val
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* @return NONE
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*/
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void ClkDisDpllAutoCalibration(uint16_t DefaultNdac);
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/**
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* @brief enable DPLL auto calibration function
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* @param NONE
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* @return DefaultNdac a average val for NDAC
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*/
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uint16_t ClkEnableAutoCalibrationDpll(void);
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/**
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* @brief generate 12M or 16M CLK
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* @param Mode:
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* 0 clk 12M
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* 1 clk 16m
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* @return NONE
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*/
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void Clk12MOr16MGenerate(uint8_t Mode);
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/**
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* @brief clk switch from dpll to rc48m
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* clk switch during working not por
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* @param NONE
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* @return NONE
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*/
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void ClkSwitchDpllToRc(void);
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/**
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* @brief clk switch from rc48m to dpll
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* clk switch during working not por
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* @param NONE
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* @return NONE
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*/
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void ClkSwitchRcToDpll(void);
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/**
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* @brief DPLL close, for low power
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* @param NONE
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* @return NONE
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*/
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void ClkDpllClose(void);
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/**
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* @brief get system clock selection during clock switch
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* @param NONE
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* @return Mode:
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* 0 use sys 96M clk
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* 1 use sys 80M clk
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*/
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char ClkSysClkSelGet(void);
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/**
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* @brief during working switch sys clk
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* @param Mode:
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* 0 use PLL 60MHz
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* 1 use sys clk
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* 2 use PLL 80MHz
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* 3 use PLL 48MHz
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* @return NONE
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*/
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char ClkFshcClkSelGet(void);
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/**
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* @brief during working switch sys clk
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* @param Mode:
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* 0 use sys 96M clk
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* 1 use sys 80M clk
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* @return NONE
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*/
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void ClkSysClkSel(uint8_t Mode);
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/**
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* @brief sys clk div set
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* @param DivVal(1~255):
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* 1 no div
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* 2 divided 2
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* ...
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* 256 divided 256
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* only support divide the frequency by even
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* @return NONE
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*/
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void ClkModuleDivSet(uint32_t DivVal);
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/**
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* @brief get sys div clk coefficient
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* @param NONE
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* @return sys div clk coefficient
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*/
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uint32_t ClkModuleDivGet(void);
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/**
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* @brief sys clk div disable
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* @param NONE
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* @return NONE
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*/
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void ClkModuleDivDis(void);
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/**
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* @brief Set the Frequency of MCLK at each sampling rate.
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* @Param SampleRate support nine
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* @Param Mode Clocking mode(1: USB mode, 0: Normal mode)
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* @return NONE
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*/
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void ClkMclkSelBySampleRate(uint32_t SampleRate, uint8_t Mode);
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/**
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* @brief after osc32k is working,use osc32k check rc48m,make sure sys can get correct freq at any time
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* @param NONE
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* @return !0 current RC freq, 0 means is time out
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*/
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uint32_t ClkUseOsc32kCheckRc48m(void);
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/**
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* @brief get clk current status
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* @param NONE
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* @return current clk status
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*/
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uint32_t ClkGetCurrentSysClkFreq(void);
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/**
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* @brief get clk current status
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* @param NONE
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* @return 1:DPLL MODE 0:RC48M mode
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*/
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uint32_t ClkCurrentClkModeGet(void);
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/**
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* @brief osc32k no need ext capacitance set
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* @param CapacityXiVal range:[0,15],step=2.587pf.base=12.8pf
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* @param CapacityXoVal range:[0,15],step=2.587pf.base=12.8pf
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* @return NONE
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*/
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void ClkOsc32kNoNeedExtCapacitanceSet(uint8_t CapacityXiVal, uint8_t CapacityXoVal);
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/**
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* @brief set osc power mode
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* @param Current range:[0,7],adjust current, default 7 is min,0 is the max
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* @return None
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*/
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void ClkOscPowerModeSel(uint8_t Current);
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/**
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* @brief RC48M trim frequency calibrated by 1MHz output
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* @param NONE
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* @return 0:no 1MHz calibration output,otherwise return RC48M actual frequency after 1MHz calibration
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*/
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int RC48MHzTrimBy1MHz(void);
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#ifdef __cplusplus
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}
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#endif//__cplusplus
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#endif
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