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258 lines
10 KiB
C
258 lines
10 KiB
C
/**
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******************************************************************************
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* @file stm32f2xx.h
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* @author MCD Application Team
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* @version V1.1.3
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* @date 05-March-2012
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F2xx devices.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_STDPERIPH_DRIVER"
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* - To change few application-specific parameters such as the HSE
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* crystal frequency
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f2xx
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* @{
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*/
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#ifndef __STM32F2xx_H
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#define __STM32F2xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/* Uncomment the line below according to the target STM32 device used in your
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application
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*/
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#if !defined (STM32F2XX)
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#define STM32F2XX
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (STM32F2XX)
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#error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)"
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#endif
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#if !defined (USE_STDPERIPH_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_STDPERIPH_DRIVER*/
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#endif /* USE_STDPERIPH_DRIVER */
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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used in your application
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Tip: To avoid modifying this file each time you need to use different HSE, you
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can define the HSE value in your toolchain compiler preprocessor.
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)26000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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*/
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#endif /* HSE_STARTUP_TIMEOUT */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief STM32F2XX Standard Peripherals Library version number V1.1.3
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*/
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#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
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#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
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|(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
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|(__STM32F2XX_STDPERIPH_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
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#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */
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#define __NVIC_PRIO_BITS 3 /*!< STM32F2XX uses 3 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @brief STM32F2XX Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** STM32 specific Interrupt Numbers **********************************************************************/
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GPIO_IRQn = 0, /*!< Window WatchDog Interrupt */
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RTC_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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IR_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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FUART_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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BUART_IRQn = 4, /*!< FLASH global Interrupt */
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PWC_IRQn = 5, /*!< RCC global Interrupt */
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TIM0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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USB_IRQn = 7, /*!< EXTI Line1 Interrupt */
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DMA_CH0_IRQn = 8, /*!< EXTI Line2 Interrupt */
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DMA_CH1_IRQn = 9, /*!< EXTI Line3 Interrupt */
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AUDIO_DECODER_IRQn = 10, /*!< EXTI Line4 Interrupt */
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SPIS_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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SPIN_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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SPIM_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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TIM1_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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WATCHDOG_IRQn = 15 /*!< DMA1 Stream 4 global Interrupt */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm3.h"
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#include <stdint.h>
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/** @addtogroup Exported_types
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* @{
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*/
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/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef const int32_t sc32; /*!< Read Only */
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typedef const int16_t sc16; /*!< Read Only */
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typedef const int8_t sc8; /*!< Read Only */
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typedef __IO int32_t vs32;
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typedef __IO int16_t vs16;
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typedef __IO int8_t vs8;
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typedef __I int32_t vsc32; /*!< Read Only */
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typedef __I int16_t vsc16; /*!< Read Only */
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typedef __I int8_t vsc8; /*!< Read Only */
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef const uint32_t uc32; /*!< Read Only */
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typedef const uint16_t uc16; /*!< Read Only */
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typedef const uint8_t uc8; /*!< Read Only */
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typedef __IO uint32_t vu32;
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typedef __IO uint16_t vu16;
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typedef __IO uint8_t vu8;
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typedef __I uint32_t vuc32; /*!< Read Only */
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typedef __I uint16_t vuc16; /*!< Read Only */
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typedef __I uint8_t vuc8; /*!< Read Only */
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Peripheral_registers_structures
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* @{
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*/
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/**
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* @brief Analog to Digital Converter
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32F2xx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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