mirror of
https://github.com/oopuuu/zTC1.git
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158 lines
4.1 KiB
INI
158 lines
4.1 KiB
INI
#
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# UNPUBLISHED PROPRIETARY SOURCE CODE
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# Copyright (c) 2016 MXCHIP Inc.
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#
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# The contents of this file may not be disclosed to third parties, copied or
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# duplicated in any form, in whole or in part, without the prior written
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# permission of MXCHIP Corporation.
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#
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# script for stm32f4xx
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source [find mico-os/makefiles/OpenOCD/interface/swj-dp.tcl]
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source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]
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set CHIP_FLASH_START 0x08000000
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set CHIP_RAM_START 0x20000000
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 1MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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adapter_khz 10000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0090
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# Section 38.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID] } {
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0090
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# Section 38.6.2
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# STM32F405xx/07xx and STM32F415xx/17xx
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set _BSTAPID1 0x06413041
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# STM32F42xxx and STM32F43xxx
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set _BSTAPID2 0x06419041
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# See STM Document RM0368 (Rev. 3)
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# STM32F401B/C
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set _BSTAPID3 0x06423041
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# STM32F401D/E
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set _BSTAPID4 0x06433041
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# See STM Document RM0383 (Rev 2)
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# STM32F411
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set _BSTAPID5 0x06431041
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
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-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
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-expected-id $_BSTAPID4 -expected-id $_BSTAPID5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME -rtos auto
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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#Reset target when gdb attaches
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$_TARGETNAME configure -event gdb-attach { reset halt; sleep 1; mww 0xE0042004 3; mww 0xE0042008 0xffffffff }
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#shutdown OpenOCD daemon when gdb detaches
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$_TARGETNAME configure -event gdb-detach { mww 0xE0042008 0x00000000; reset halt; sleep 5; resume; shutdown }
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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#cortex_m3 reset_config srst
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################################################################################
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
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mww 0xE0042008 0x00001800
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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proc jtag_init {} {
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global _TARGETNAME
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# assert both resets; equivalent to power-on reset
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jtag_reset 1 1
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sleep 1
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jtag_reset 0 1
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# Examine scanchain
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jtag arp_init
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$_TARGETNAME arp_examine
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# Force STM32 to allow debugging whilst sleeping and in stop-mode
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mww 0xE0042004 3
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# Set flags to cause timer based peripherals to stop during breakpoints.
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mww 0xE0042008 0xffffffff
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reset halt
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poll on
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}
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