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107 lines
4.6 KiB
C
107 lines
4.6 KiB
C
/**
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******************************************************************************
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* @file spi_flash_internal.c
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* @author William Xu
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* @version V1.0.0
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* @date 16-Sep-2014
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* @brief This file provides all the headers of flash operation functions.
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******************************************************************************
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*
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#ifndef INCLUDED_SPI_FLASH_INTERNAL_H
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#define INCLUDED_SPI_FLASH_INTERNAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "spi_flash.h"
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#include <stdint.h>
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/* Status Register bit definitions */
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#define SFLASH_STATUS_REGISTER_BUSY ( 0x01 )
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#define SFLASH_STATUS_REGISTER_WRITE_ENABLED ( 0x02 )
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#define SFLASH_STATUS_REGISTER_BLOCK_PROTECTED_0 ( 0x04 )
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#define SFLASH_STATUS_REGISTER_BLOCK_PROTECTED_1 ( 0x08 )
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#define SFLASH_STATUS_REGISTER_BLOCK_PROTECTED_2 ( 0x10 ) /* SST Only */
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#define SFLASH_STATUS_REGISTER_BLOCK_PROTECTED_3 ( 0x20 ) /* SST Only */
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#define SFLASH_STATUS_REGISTER_AUTO_ADDRESS_INCREMENT ( 0x40 ) /* SST Only */
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#define SFLASH_STATUS_REGISTER_BLOCK_PROTECT_BITS_READ_ONLY ( 0x80 ) /* SST Only */
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/* Command definitions */
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typedef enum
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{
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SFLASH_WRITE_STATUS_REGISTER = 0x01, /* WRSR */
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SFLASH_WRITE = 0x02,
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SFLASH_QUAD_WRITE = 0x38,
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SFLASH_READ = 0x03,
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SFLASH_QUAD_READ = 0xEB,
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SFLASH_WRITE_DISABLE = 0x04, /* WRDI */
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SFLASH_READ_STATUS_REGISTER = 0x05, /* RDSR */
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SFLASH_WRITE_ENABLE = 0x06, /* WREN */
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SFLASH_FAST_READ = 0x0B,
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SFLASH_SECTOR_ERASE = 0x20, /* SE */
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SFLASH_BLOCK_ERASE_MID = 0x52, /* SE */
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SFLASH_BLOCK_ERASE_LARGE = 0xD8, /* SE */
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SFLASH_READ_ID1 = 0x90, /* data size varies */
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SFLASH_READ_ID2 = 0xAB, /* data size varies */
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SFLASH_READ_JEDEC_ID = 0x9F, /* RDID */
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SFLASH_CHIP_ERASE1 = 0x60, /* CE */
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SFLASH_CHIP_ERASE2 = 0xC7, /* CE */
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SFLASH_ENABLE_WRITE_STATUS_REGISTER = 0x50, /* EWSR - SST only */
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SFLASH_READ_SECURITY_REGISTER = 0x2B, /* RDSCUR - Macronix only */
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SFLASH_WRITE_SECURITY_REGISTER = 0x2F, /* WRSCUR - Macronix only */
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SFLASH_ENTER_SECURED_OTP = 0xB1, /* ENSO - Macronix only */
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SFLASH_EXIT_SECURED_OTP = 0xC1, /* EXSO - Macronix only */
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SFLASH_DEEP_POWER_DOWN = 0xB9, /* DP - Macronix only */
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SFLASH_RELEASE_DEEP_POWER_DOWN = 0xAB, /* RDP - Macronix only */
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} sflash_command_t;
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#define SFLASH_DUMMY_BYTE ( 0xA5 )
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#define DUMMY_CLOCK_CYCLES_READ_QUAD 0x06
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#define SFLASH_MANUFACTURER( id ) ( ( (id) & 0x00ff0000 ) >> 16 )
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#define SFLASH_MANUFACTURER_SST ( (uint8_t) 0xBF )
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#define SFLASH_MANUFACTURER_MACRONIX ( (uint8_t) 0xC2 )
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#define SFLASH_MANUFACTURER_EON ( (uint8_t) 0x1C )
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#define SFLASH_MANUFACTURER_WINBOND ( (uint8_t) 0xEF )
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#define SFLASH_ID_MX25L8006E ( (uint32_t) 0xC22014 )
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#define SFLASH_ID_MX25L1606E ( (uint32_t) 0xC22015 )
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#define SFLASH_ID_SST25VF080B ( (uint32_t) 0xBF258E )
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#define SFLASH_ID_EN25QH16 ( (uint32_t) 0x1C3015 )
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#define SFLASH_ID_W25X80AVSIG ( (uint32_t) 0xEF3014 )
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typedef struct
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{
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unsigned char id[3];
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} device_id_t;
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int sflash_read_ID ( const sflash_handle_t* handle, void* data_addr );
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int sflash_read_status_register ( const sflash_handle_t* handle, void* dest_addr );
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int sflash_write_status_register( const sflash_handle_t* handle, char value );
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int generic_sflash_command ( const sflash_handle_t* handle, sflash_command_t cmd, unsigned long num_initial_parameter_bytes, /*@null@*/ /*@observer@*/ const void* parameter_bytes, unsigned long num_data_bytes, /*@null@*/ /*@observer@*/ const void* const data_MOSI, /*@null@*/ /*@out@*/ /*@dependent@*/ void* const data_MISO );
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#ifdef __cplusplus
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}
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#endif
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#endif /* INCLUDED_SPI_FLASH_INTERNAL_H */
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