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https://github.com/oopuuu/zTC1.git
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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
This commit is contained in:
OOP
674
mico-os/platform/MCU/STM32F4xx/peripherals/platform_uart.c
Normal file
674
mico-os/platform/MCU/STM32F4xx/peripherals/platform_uart.c
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@@ -0,0 +1,674 @@
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/**
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******************************************************************************
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* @file platform_uart.c
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provide UART driver functions.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "platform.h"
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#include "platform_peripheral.h"
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#include "debug.h"
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/******************************************************
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* Constants
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******************************************************/
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#define DMA_INTERRUPT_FLAGS ( DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_FE )
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/******************************************************
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* Enumerations
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******************************************************/
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/******************************************************
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* Type Definitions
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******************************************************/
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/******************************************************
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* Structures
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******************************************************/
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/******************************************************
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* Variables Definitions
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******************************************************/
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/* UART alternate functions */
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static const uint8_t uart_alternate_functions[NUMBER_OF_UART_PORTS] =
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{
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[0] = GPIO_AF_USART1,
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[1] = GPIO_AF_USART2,
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[2] = GPIO_AF_USART3,
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[3] = GPIO_AF_UART4,
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[4] = GPIO_AF_UART5,
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[5] = GPIO_AF_USART6,
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};
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/* UART peripheral clock functions */
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static const platform_peripheral_clock_function_t uart_peripheral_clock_functions[NUMBER_OF_UART_PORTS] =
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{
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[0] = RCC_APB2PeriphClockCmd,
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[1] = RCC_APB1PeriphClockCmd,
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[2] = RCC_APB1PeriphClockCmd,
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[3] = RCC_APB1PeriphClockCmd,
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[4] = RCC_APB1PeriphClockCmd,
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[5] = RCC_APB2PeriphClockCmd,
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};
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/* UART peripheral clocks */
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static const uint32_t uart_peripheral_clocks[NUMBER_OF_UART_PORTS] =
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{
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[0] = RCC_APB2Periph_USART1,
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[1] = RCC_APB1Periph_USART2,
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[2] = RCC_APB1Periph_USART3,
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[3] = RCC_APB1Periph_UART4,
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[4] = RCC_APB1Periph_UART5,
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[5] = RCC_APB2Periph_USART6,
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};
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/* UART interrupt vectors */
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#if defined (STM32F401xx) || defined (STM32F411xE)
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static const IRQn_Type uart_irq_vectors[NUMBER_OF_UART_PORTS] =
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{
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[0] = USART1_IRQn,
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[1] = USART2_IRQn,
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[2] = (IRQn_Type)0xFF,
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[3] = (IRQn_Type)0xFF,
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[4] = (IRQn_Type)0xFF,
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[5] = USART6_IRQn,
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};
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#elif defined (STM32F412xG)
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static const IRQn_Type uart_irq_vectors[NUMBER_OF_UART_PORTS] =
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{
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[0] = USART1_IRQn,
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[1] = USART2_IRQn,
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[2] = USART3_IRQn,
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[3] = (IRQn_Type)0xFF,
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[4] = (IRQn_Type)0xFF,
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[5] = USART6_IRQn,
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};
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#else
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static const IRQn_Type uart_irq_vectors[NUMBER_OF_UART_PORTS] =
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{
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[0] = USART1_IRQn,
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[1] = USART2_IRQn,
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[2] = USART3_IRQn,
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[3] = UART4_IRQn,
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[4] = UART5_IRQn,
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[5] = USART6_IRQn,
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};
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#endif
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/******************************************************
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* Static Function Declarations
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******************************************************/
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static OSStatus receive_bytes ( platform_uart_driver_t* driver, void* data, uint32_t size, uint32_t timeout );
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static uint32_t get_dma_irq_status ( DMA_Stream_TypeDef* stream );
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static void clear_dma_interrupts( DMA_Stream_TypeDef* stream, uint32_t flags );
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/******************************************************
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* Function Definitions
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******************************************************/
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OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
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{
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DMA_InitTypeDef dma_init_structure;
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USART_InitTypeDef uart_init_structure;
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uint32_t uart_number;
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
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require_action_quiet( (optional_ring_buffer == NULL) || ((optional_ring_buffer->buffer != NULL ) && (optional_ring_buffer->size != 0)), exit, err = kParamErr);
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uart_number = platform_uart_get_port_number( peripheral->port );
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driver->rx_size = 0;
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driver->tx_size = 0;
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driver->last_transmit_result = kNoErr;
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driver->last_receive_result = kNoErr;
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driver->peripheral = (platform_uart_t*)peripheral;
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if( driver->initialized == false )
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{
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mico_rtos_init_semaphore( &driver->tx_complete, 1 );
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mico_rtos_init_semaphore( &driver->rx_complete, 1 );
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mico_rtos_init_mutex ( &driver->tx_mutex );
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/* Configure TX and RX pin_mapping */
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platform_gpio_set_alternate_function( peripheral->pin_tx->port, peripheral->pin_tx->pin_number, GPIO_OType_PP, GPIO_PuPd_UP, uart_alternate_functions[ uart_number ] );
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platform_gpio_set_alternate_function( peripheral->pin_rx->port, peripheral->pin_rx->pin_number, GPIO_OType_PP, GPIO_PuPd_UP, uart_alternate_functions[ uart_number ] );
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}
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if ( ( peripheral->pin_cts != NULL ) && ( config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS ) )
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{
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platform_gpio_set_alternate_function( peripheral->pin_cts->port, peripheral->pin_cts->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
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}
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if ( ( peripheral->pin_rts != NULL ) && ( config->flow_control == FLOW_CONTROL_RTS || config->flow_control == FLOW_CONTROL_CTS_RTS ) )
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{
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platform_gpio_set_alternate_function( peripheral->pin_rts->port, peripheral->pin_rts->pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, uart_alternate_functions[ uart_number ] );
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}
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/* Enable UART peripheral clock */
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uart_peripheral_clock_functions[ uart_number ]( uart_peripheral_clocks[ uart_number ], ENABLE );
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uart_init_structure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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uart_init_structure.USART_BaudRate = config->baud_rate;
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uart_init_structure.USART_WordLength = ( ( config->data_width == DATA_WIDTH_9BIT ) || ( ( config->data_width == DATA_WIDTH_8BIT ) && ( config->parity != NO_PARITY ) ) ) ? USART_WordLength_9b : USART_WordLength_8b;
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uart_init_structure.USART_StopBits = ( config->stop_bits == STOP_BITS_1 ) ? USART_StopBits_1 : USART_StopBits_2;
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switch ( config->parity )
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{
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case NO_PARITY:
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uart_init_structure.USART_Parity = USART_Parity_No;
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break;
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case EVEN_PARITY:
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uart_init_structure.USART_Parity = USART_Parity_Even;
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break;
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case ODD_PARITY:
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uart_init_structure.USART_Parity = USART_Parity_Odd;
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break;
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default:
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err = kParamErr;
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goto exit;
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}
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switch ( config->flow_control )
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{
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case FLOW_CONTROL_DISABLED:
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uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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break;
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case FLOW_CONTROL_CTS:
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uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_CTS;
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break;
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case FLOW_CONTROL_RTS:
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uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS;
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driver->is_flow_control = true;
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break;
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case FLOW_CONTROL_CTS_RTS:
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uart_init_structure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
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driver->is_flow_control = true;
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break;
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default:
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err = kParamErr;
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goto exit;
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}
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/* Initialise USART peripheral */
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USART_DeInit( peripheral->port );
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USART_Init( peripheral->port, &uart_init_structure );
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/**************************************************************************
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* Initialise STM32 DMA registers
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* Note: If DMA is used, USART interrupt isn't enabled.
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**************************************************************************/
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/* Enable DMA peripheral clock */
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if ( peripheral->tx_dma_config.controller == DMA1 )
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{
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RCC->AHB1ENR |= RCC_AHB1Periph_DMA1;
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}
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else
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{
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RCC->AHB1ENR |= RCC_AHB1Periph_DMA2;
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}
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/* Fill init structure with common DMA settings */
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dma_init_structure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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dma_init_structure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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dma_init_structure.DMA_Priority = DMA_Priority_VeryHigh;
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dma_init_structure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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dma_init_structure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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dma_init_structure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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dma_init_structure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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if ( config->data_width == DATA_WIDTH_9BIT )
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{
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dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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}
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else
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{
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dma_init_structure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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dma_init_structure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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}
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/* Initialise TX DMA */
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DMA_DeInit( peripheral->tx_dma_config.stream );
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dma_init_structure.DMA_Channel = peripheral->tx_dma_config.channel;
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dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &peripheral->port->DR;
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dma_init_structure.DMA_Memory0BaseAddr = (uint32_t) 0;
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dma_init_structure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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dma_init_structure.DMA_BufferSize = 0xFFFF; // This parameter will be configured during communication
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dma_init_structure.DMA_Mode = DMA_Mode_Normal;
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DMA_Init( peripheral->tx_dma_config.stream, &dma_init_structure );
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/* Initialise RX DMA */
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DMA_DeInit( peripheral->rx_dma_config.stream );
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dma_init_structure.DMA_Channel = peripheral->rx_dma_config.channel;
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dma_init_structure.DMA_PeripheralBaseAddr = (uint32_t) &peripheral->port->DR;
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dma_init_structure.DMA_Memory0BaseAddr = (uint32_t) 0;
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dma_init_structure.DMA_DIR = DMA_DIR_PeripheralToMemory;
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dma_init_structure.DMA_BufferSize = 0xFFFF; // This parameter will be configured during communication
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dma_init_structure.DMA_Mode = DMA_Mode_Normal;
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DMA_Init( peripheral->rx_dma_config.stream, &dma_init_structure );
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/**************************************************************************
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* Initialise STM32 DMA interrupts
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**************************************************************************/
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/* Configure TX DMA interrupt on Cortex-M3 */
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NVIC_EnableIRQ( peripheral->tx_dma_config.irq_vector );
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/* Enable TC (transfer complete) and TE (transfer error) interrupts on source */
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clear_dma_interrupts( peripheral->tx_dma_config.stream, peripheral->tx_dma_config.complete_flags | peripheral->tx_dma_config.error_flags );
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DMA_ITConfig( peripheral->tx_dma_config.stream, DMA_INTERRUPT_FLAGS, ENABLE );
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/* Enable USART interrupt vector in Cortex-M3 */
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NVIC_EnableIRQ( uart_irq_vectors[uart_number] );
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USART_DMACmd( driver->peripheral->port, USART_DMAReq_Tx, DISABLE );
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/* Enable USART */
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USART_Cmd( peripheral->port, ENABLE );
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/* Enable both transmit and receive */
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peripheral->port->CR1 |= USART_CR1_TE;
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peripheral->port->CR1 |= USART_CR1_RE;
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/* Setup ring buffer */
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if ( optional_ring_buffer != NULL )
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{
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/* Note that the ring_buffer should've been initialised first */
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driver->rx_buffer = optional_ring_buffer;
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driver->rx_size = 0;
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driver->peripheral->rx_dma_config.stream->CR |= DMA_SxCR_CIRC;
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// Enabled individual byte interrupts so progress can be updated
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USART_ClearITPendingBit( driver->peripheral->port, USART_IT_RXNE );
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USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, ENABLE );
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}
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else
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{
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/* Not using ring buffer. Configure RX DMA interrupt on Cortex-M3 */
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NVIC_EnableIRQ( peripheral->rx_dma_config.irq_vector );
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/* Enable TC (transfer complete) and TE (transfer error) interrupts on source */
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clear_dma_interrupts( peripheral->rx_dma_config.stream, peripheral->rx_dma_config.complete_flags | peripheral->rx_dma_config.error_flags );
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DMA_ITConfig( peripheral->rx_dma_config.stream, DMA_INTERRUPT_FLAGS, ENABLE );
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}
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driver->initialized = true;
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_uart_deinit( platform_uart_driver_t* driver )
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{
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uint8_t uart_number;
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( ( driver != NULL ), exit, err = kParamErr);
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uart_number = platform_uart_get_port_number( driver->peripheral->port );
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/* Disable USART */
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USART_Cmd( driver->peripheral->port, DISABLE );
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|
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/* Deinitialise USART */
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USART_DeInit( driver->peripheral->port );
|
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|
||||
/**************************************************************************
|
||||
* De-initialise STM32 DMA and interrupt
|
||||
**************************************************************************/
|
||||
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/* Deinitialise DMA streams */
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DMA_DeInit( driver->peripheral->tx_dma_config.stream );
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DMA_DeInit( driver->peripheral->rx_dma_config.stream );
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|
||||
/* Disable TC (transfer complete) interrupt at the source */
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DMA_ITConfig( driver->peripheral->tx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE );
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||||
DMA_ITConfig( driver->peripheral->rx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE );
|
||||
|
||||
/* Disable transmit DMA interrupt at Cortex-M3 */
|
||||
NVIC_DisableIRQ( driver->peripheral->tx_dma_config.irq_vector );
|
||||
|
||||
/**************************************************************************
|
||||
* De-initialise STM32 USART interrupt
|
||||
**************************************************************************/
|
||||
|
||||
USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, DISABLE );
|
||||
|
||||
/* Disable UART interrupt vector on Cortex-M3 */
|
||||
NVIC_DisableIRQ( driver->peripheral->rx_dma_config.irq_vector );
|
||||
|
||||
/* Disable registers clocks */
|
||||
uart_peripheral_clock_functions[uart_number]( uart_peripheral_clocks[uart_number], DISABLE );
|
||||
|
||||
mico_rtos_deinit_semaphore( &driver->rx_complete );
|
||||
mico_rtos_deinit_semaphore( &driver->tx_complete );
|
||||
mico_rtos_deinit_mutex( &driver->tx_mutex );
|
||||
driver->rx_size = 0;
|
||||
driver->tx_size = 0;
|
||||
driver->last_transmit_result = kNoErr;
|
||||
driver->last_receive_result = kNoErr;
|
||||
driver->initialized = false;
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_uart_transmit_bytes( platform_uart_driver_t* driver, const uint8_t* data_out, uint32_t size )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
platform_mcu_powersave_disable();
|
||||
|
||||
mico_rtos_lock_mutex( &driver->tx_mutex );
|
||||
|
||||
require_action_quiet( ( driver != NULL ) && ( data_out != NULL ) && ( size != 0 ), exit, err = kParamErr);
|
||||
|
||||
/* Clear interrupt status before enabling DMA otherwise error occurs immediately */
|
||||
clear_dma_interrupts( driver->peripheral->tx_dma_config.stream, driver->peripheral->tx_dma_config.complete_flags | driver->peripheral->tx_dma_config.error_flags );
|
||||
|
||||
/* Init DMA parameters and variables */
|
||||
driver->last_transmit_result = kGeneralErr;
|
||||
driver->tx_size = size;
|
||||
driver->peripheral->tx_dma_config.stream->CR &= ~(uint32_t) DMA_SxCR_CIRC;
|
||||
driver->peripheral->tx_dma_config.stream->NDTR = size;
|
||||
driver->peripheral->tx_dma_config.stream->M0AR = (uint32_t)data_out;
|
||||
|
||||
USART_DMACmd( driver->peripheral->port, USART_DMAReq_Tx, ENABLE );
|
||||
USART_ClearFlag( driver->peripheral->port, USART_FLAG_TC );
|
||||
driver->peripheral->tx_dma_config.stream->CR |= DMA_SxCR_EN;
|
||||
|
||||
/* Wait for transmission complete */
|
||||
mico_rtos_get_semaphore( &driver->tx_complete, MICO_NEVER_TIMEOUT );
|
||||
|
||||
while ( ( driver->peripheral->port->SR & USART_SR_TC ) == 0 )
|
||||
{
|
||||
}
|
||||
|
||||
/* Disable DMA and clean up */
|
||||
USART_DMACmd( driver->peripheral->port, USART_DMAReq_Tx, DISABLE );
|
||||
driver->tx_size = 0;
|
||||
err = driver->last_transmit_result;
|
||||
|
||||
exit:
|
||||
mico_rtos_unlock_mutex( &driver->tx_mutex );
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_uart_receive_bytes( platform_uart_driver_t* driver, uint8_t* data_in, uint32_t expected_data_size, uint32_t timeout_ms )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
//platform_mcu_powersave_disable();
|
||||
|
||||
require_action_quiet( ( driver != NULL ) && ( data_in != NULL ) && ( expected_data_size != 0 ), exit, err = kParamErr);
|
||||
|
||||
mico_rtos_get_semaphore( &driver->rx_complete, 0 );
|
||||
|
||||
if ( driver->rx_buffer != NULL)
|
||||
{
|
||||
if( ( driver->is_flow_control == true ) && ( driver->is_recv_over_flow == true ) )
|
||||
{
|
||||
driver->is_recv_over_flow = false;
|
||||
USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, ENABLE );
|
||||
}
|
||||
|
||||
while ( expected_data_size != 0 )
|
||||
{
|
||||
uint32_t transfer_size = MIN( driver->rx_buffer->size / 2, expected_data_size );
|
||||
|
||||
/* Set rx_size and wait in rx_complete semaphore until data reaches rx_size or timeout occurs */
|
||||
driver->last_receive_result = kNoErr;
|
||||
driver->rx_size = transfer_size;
|
||||
|
||||
/* Check if ring buffer already contains the required amount of data. */
|
||||
if ( transfer_size > ring_buffer_used_space( driver->rx_buffer ) )
|
||||
{
|
||||
err = mico_rtos_get_semaphore( &driver->rx_complete, timeout_ms );
|
||||
|
||||
/* Reset rx_size to prevent semaphore being set while nothing waits for the data */
|
||||
driver->rx_size = 0;
|
||||
|
||||
if( err != kNoErr )
|
||||
goto exit;
|
||||
}else {
|
||||
driver->rx_size = 0;
|
||||
}
|
||||
err = driver->last_receive_result;
|
||||
expected_data_size -= transfer_size;
|
||||
|
||||
// Grab data from the buffer
|
||||
do
|
||||
{
|
||||
uint8_t* available_data;
|
||||
uint32_t bytes_available;
|
||||
|
||||
ring_buffer_get_data( driver->rx_buffer, &available_data, &bytes_available );
|
||||
bytes_available = MIN( bytes_available, transfer_size );
|
||||
memcpy( data_in, available_data, bytes_available );
|
||||
transfer_size -= bytes_available;
|
||||
data_in = ( (uint8_t*) data_in + bytes_available );
|
||||
ring_buffer_consume( driver->rx_buffer, bytes_available );
|
||||
} while ( transfer_size != 0 );
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = receive_bytes( driver, data_in, expected_data_size, timeout_ms );
|
||||
}
|
||||
exit:
|
||||
//platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
static OSStatus receive_bytes( platform_uart_driver_t* driver, void* data, uint32_t size, uint32_t timeout )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
if ( driver->rx_buffer != NULL )
|
||||
{
|
||||
driver->peripheral->rx_dma_config.stream->CR |= DMA_SxCR_CIRC;
|
||||
|
||||
// Enabled individual byte interrupts so progress can be updated
|
||||
USART_ClearITPendingBit( driver->peripheral->port, USART_IT_RXNE );
|
||||
USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, ENABLE );
|
||||
}
|
||||
else
|
||||
{
|
||||
driver->rx_size = size;
|
||||
driver->peripheral->rx_dma_config.stream->CR &= ~(uint32_t) DMA_SxCR_CIRC;
|
||||
}
|
||||
|
||||
clear_dma_interrupts( driver->peripheral->rx_dma_config.stream, driver->peripheral->rx_dma_config.complete_flags | driver->peripheral->rx_dma_config.error_flags );
|
||||
|
||||
driver->peripheral->rx_dma_config.stream->NDTR = size;
|
||||
driver->peripheral->rx_dma_config.stream->M0AR = (uint32_t)data;
|
||||
driver->peripheral->rx_dma_config.stream->CR |= DMA_SxCR_EN;
|
||||
USART_DMACmd( driver->peripheral->port, USART_DMAReq_Rx, ENABLE );
|
||||
|
||||
if ( timeout > 0 )
|
||||
{
|
||||
err = mico_rtos_get_semaphore( &driver->rx_complete, timeout );
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
uint32_t platform_uart_get_length_in_buffer( platform_uart_driver_t* driver )
|
||||
{
|
||||
return ring_buffer_used_space( driver->rx_buffer );
|
||||
}
|
||||
|
||||
static void clear_dma_interrupts( DMA_Stream_TypeDef* stream, uint32_t flags )
|
||||
{
|
||||
if ( stream <= DMA1_Stream3 )
|
||||
{
|
||||
DMA1->LIFCR |= flags;
|
||||
}
|
||||
else if ( stream <= DMA1_Stream7 )
|
||||
{
|
||||
DMA1->HIFCR |= flags;
|
||||
}
|
||||
else if ( stream <= DMA2_Stream3 )
|
||||
{
|
||||
DMA2->LIFCR |= flags;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA2->HIFCR |= flags;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t get_dma_irq_status( DMA_Stream_TypeDef* stream )
|
||||
{
|
||||
if ( stream <= DMA1_Stream3 )
|
||||
{
|
||||
return DMA1->LISR;
|
||||
}
|
||||
else if ( stream <= DMA1_Stream7 )
|
||||
{
|
||||
return DMA1->HISR;
|
||||
}
|
||||
else if ( stream <= DMA2_Stream3 )
|
||||
{
|
||||
return DMA2->LISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return DMA2->HISR;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t platform_uart_get_port_number( USART_TypeDef* uart )
|
||||
{
|
||||
if ( uart == USART1 )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
else if ( uart == USART2 )
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
else if ( uart == USART3 )
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
else if ( uart == UART4 )
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
else if ( uart == UART5 )
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
else if ( uart == USART6 )
|
||||
{
|
||||
return 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/******************************************************
|
||||
* Interrupt Service Routines
|
||||
******************************************************/
|
||||
|
||||
|
||||
void platform_uart_irq( platform_uart_driver_t* driver )
|
||||
{
|
||||
uint8_t recv_byte = 0;
|
||||
platform_uart_port_t* uart = (platform_uart_port_t*) driver->peripheral->port;
|
||||
|
||||
/* Receive new data */
|
||||
if ( USART_GetITStatus( uart, USART_IT_RXNE ) == SET )
|
||||
{
|
||||
if ( ring_buffer_is_full( driver->rx_buffer ) == 0 )
|
||||
{
|
||||
recv_byte = USART_ReceiveData( uart );
|
||||
ring_buffer_write( driver->rx_buffer, &recv_byte, 1 );
|
||||
if ( ( driver->rx_size > 0 ) && ( ring_buffer_used_space( driver->rx_buffer ) >= driver->rx_size ) )
|
||||
{
|
||||
mico_rtos_set_semaphore( &driver->rx_complete );
|
||||
driver->rx_size = 0;
|
||||
}
|
||||
} else
|
||||
{
|
||||
if( driver->is_flow_control == true ){
|
||||
USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, DISABLE );
|
||||
driver->is_recv_over_flow = true;
|
||||
}else{
|
||||
USART_ReceiveData( uart );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void platform_uart_tx_dma_irq( platform_uart_driver_t* driver )
|
||||
{
|
||||
if ( ( get_dma_irq_status( driver->peripheral->tx_dma_config.stream ) & driver->peripheral->tx_dma_config.complete_flags ) != 0 )
|
||||
{
|
||||
clear_dma_interrupts( driver->peripheral->tx_dma_config.stream, driver->peripheral->tx_dma_config.complete_flags );
|
||||
driver->last_transmit_result = kNoErr;
|
||||
}
|
||||
|
||||
if ( ( get_dma_irq_status( driver->peripheral->tx_dma_config.stream ) & driver->peripheral->tx_dma_config.error_flags ) != 0 )
|
||||
{
|
||||
clear_dma_interrupts( driver->peripheral->tx_dma_config.stream, driver->peripheral->tx_dma_config.error_flags );
|
||||
driver->last_transmit_result = kGeneralErr;
|
||||
}
|
||||
|
||||
if ( driver->tx_size > 0 )
|
||||
{
|
||||
/* Set semaphore regardless of result to prevent waiting thread from locking up */
|
||||
mico_rtos_set_semaphore( &driver->tx_complete );
|
||||
}
|
||||
}
|
||||
|
||||
void platform_uart_rx_dma_irq( platform_uart_driver_t* driver )
|
||||
{
|
||||
if ( ( get_dma_irq_status( driver->peripheral->rx_dma_config.stream ) & driver->peripheral->rx_dma_config.complete_flags ) != 0 )
|
||||
{
|
||||
clear_dma_interrupts( driver->peripheral->rx_dma_config.stream, driver->peripheral->rx_dma_config.complete_flags );
|
||||
driver->last_receive_result = kNoErr;
|
||||
}
|
||||
|
||||
if ( ( get_dma_irq_status( driver->peripheral->rx_dma_config.stream ) & driver->peripheral->rx_dma_config.error_flags ) != 0 )
|
||||
{
|
||||
clear_dma_interrupts( driver->peripheral->rx_dma_config.stream, driver->peripheral->rx_dma_config.error_flags );
|
||||
driver->last_receive_result = kGeneralErr;
|
||||
}
|
||||
|
||||
if ( driver->rx_size > 0 )
|
||||
{
|
||||
/* Set semaphore regardless of result to prevent waiting thread from locking up */
|
||||
mico_rtos_set_semaphore( &driver->rx_complete );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user