mirror of
https://github.com/oopuuu/zTC1.git
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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
This commit is contained in:
OOP
175
mico-os/platform/MCU/STM32F4xx/GCC/app_ram.ld
Normal file
175
mico-os/platform/MCU/STM32F4xx/GCC/app_ram.ld
Normal file
@@ -0,0 +1,175 @@
|
||||
/**
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
*
|
||||
*/
|
||||
|
||||
Reset_Handler = _start;
|
||||
|
||||
ENTRY( _start );
|
||||
|
||||
/* Include memory map */
|
||||
INCLUDE memory.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Data transfer area for serial flash writing app - at start of memory */
|
||||
.sflash_trnsf :
|
||||
{
|
||||
KEEP(*(*.data_config))
|
||||
KEEP(*(*.data_transfer))
|
||||
}>SRAM AT> SRAM
|
||||
|
||||
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(512);
|
||||
link_interrupt_vectors_location = .;
|
||||
KEEP(*(*.interrupt_vector_table))
|
||||
}>SRAM AT> SRAM
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
link_code_location = .;
|
||||
KEEP(*(.text.irq ))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
link_code_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_const_variable_data_location = .;
|
||||
wifi_firmware_image_location = .;
|
||||
*(.rodata.wifi_firmware_image)
|
||||
wifi_firmware_image_end = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
link_const_variable_data_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_constructors_location = .;
|
||||
KEEP(*(.preinit_array))
|
||||
KEEP(*(.init_array))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
link_constructors_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_destructors_location = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
link_destructors_end = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
|
||||
}>SRAM AT> SRAM
|
||||
|
||||
/*
|
||||
* The .ARM.exidx and .ARM.exidx sections are used for C++ exception handling.
|
||||
* It is located here for completeness. Bare-metal ARM projects
|
||||
* typically cannot afford the overhead associated with C++
|
||||
* exceptions handling.
|
||||
*/
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = ALIGN(4);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} >SRAM AT> SRAM
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
__extab_start = ALIGN(4);
|
||||
*(.ARM.extab*)
|
||||
__extab_end = .;
|
||||
} > SRAM AT> SRAM
|
||||
|
||||
.fast : /* This section contains code that is run from RAM after being loaded from flash - functions can be put in this section with the C attribute: __attribute__ ((section (".fast"))) */
|
||||
{
|
||||
link_run_from_ram_code_flash_location = LOADADDR( .fast ); /* This is the location in flash of the code */
|
||||
link_run_from_ram_code_ram_location = .;
|
||||
*(.fast .fast.* .text.fastcode)
|
||||
link_run_from_ram_code_ram_end = .;
|
||||
}>SRAM AT> SRAM
|
||||
|
||||
.data : /* Contains the non-zero initialised global variables */
|
||||
{
|
||||
link_global_data_initial_values = LOADADDR( .data ); /* This is the location in flash of the initial values of global variables */
|
||||
link_global_data_start = .;
|
||||
*(.data*)
|
||||
link_global_data_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}>SRAM AT> SRAM
|
||||
|
||||
|
||||
.bss : /* Zero initialised memory used for zero initialised variables */
|
||||
{
|
||||
link_bss_location = ALIGN(., 4);
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
link_bss_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
|
||||
.stack : /* Contains the initial stack */
|
||||
{
|
||||
link_stack_location = ALIGN(., 4);
|
||||
*(.stack)
|
||||
. = ALIGN(MAX(link_stack_location + __STACKSIZE__ , .), 4);
|
||||
link_stack_end = .;
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.attributes*)
|
||||
*(.comment)
|
||||
*(.init)
|
||||
*(.preinit)
|
||||
*(.fini)
|
||||
*(.fini_array)
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
*(.v4_bx)
|
||||
*(.vfp11_veneer)
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.glue*)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Declare libc Heap to start at end of allocated RAM */
|
||||
|
||||
PROVIDE( _heap = link_stack_end );
|
||||
|
||||
/* End of the heap is top of RAM, aligned 8 byte */
|
||||
|
||||
PROVIDE( _eheap = ALIGN( ORIGIN( SRAM ) + LENGTH( SRAM ) - 8, 8 ) );
|
||||
PROVIDE( total_app_image_size = LOADADDR( .data ) - ORIGIN( SRAM ) + link_global_data_end - link_global_data_start );
|
||||
PROVIDE( wifi_firmware_image_size_from_link = wifi_firmware_image_end - wifi_firmware_image_location );
|
||||
|
||||
/* ThreadX aliases */
|
||||
PROVIDE( __RAM_segment_used_end__ = link_stack_end );
|
||||
PROVIDE( __tx_free_memory_start = link_stack_end );
|
||||
PROVIDE( __tx_vectors = link_interrupt_vectors_location );
|
||||
|
||||
PROVIDE( wifi_firmware_image = 0 );
|
||||
|
||||
|
||||
|
||||
152
mico-os/platform/MCU/STM32F4xx/GCC/app_with_bootloader.ld
Normal file
152
mico-os/platform/MCU/STM32F4xx/GCC/app_with_bootloader.ld
Normal file
@@ -0,0 +1,152 @@
|
||||
/**
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
*
|
||||
*/
|
||||
|
||||
Reset_Handler = _start;
|
||||
|
||||
ENTRY( _start );
|
||||
|
||||
/* Include memory map */
|
||||
INCLUDE memory.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.vectors :
|
||||
{
|
||||
link_interrupt_vectors_location = .;
|
||||
KEEP(*(*.interrupt_vector_table))
|
||||
KEEP(*(.stub_section))
|
||||
}>APP_FLASH AT> APP_FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
link_code_location = .;
|
||||
KEEP(*(.text.irq ))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
link_code_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_const_variable_data_location = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
link_const_variable_data_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_constructors_location = .;
|
||||
KEEP(*(.preinit_array))
|
||||
KEEP(*(.init_array))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
link_constructors_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_destructors_location = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
link_destructors_end = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
|
||||
}>APP_FLASH AT> APP_FLASH
|
||||
|
||||
/*
|
||||
* The .ARM.exidx and .ARM.extab sections are used for C++ exception handling.
|
||||
* It is located here for completeness. Bare-metal ARM projects
|
||||
* typically cannot afford the overhead associated with C++
|
||||
* exceptions handling.
|
||||
*/
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = ALIGN(4);
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > APP_FLASH AT> APP_FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
__extab_start = ALIGN(4);
|
||||
*(.ARM.extab*)
|
||||
__extab_end = .;
|
||||
} > APP_FLASH AT> APP_FLASH
|
||||
|
||||
.fast : /* This section contains code that is run from RAM after being loaded from flash - functions can be put in this section with the C attribute: __attribute__ ((section (".fast"))) */
|
||||
{
|
||||
link_run_from_ram_code_flash_location = LOADADDR( .fast ); /* This is the location in flash of the code */
|
||||
link_run_from_ram_code_ram_location = .;
|
||||
*(.fast .fast.* .text.fastcode)
|
||||
link_run_from_ram_code_ram_end = .;
|
||||
}> SRAM AT> APP_FLASH
|
||||
|
||||
.data : /* Contains the non-zero initialised global variables */
|
||||
{
|
||||
link_global_data_initial_values = LOADADDR( .data ); /* This is the location in flash of the initial values of global variables */
|
||||
link_global_data_start = .;
|
||||
*(.data*)
|
||||
link_global_data_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}> SRAM AT> APP_FLASH
|
||||
|
||||
|
||||
.bss : /* Zero initialised memory used for zero initialised variables */
|
||||
{
|
||||
link_bss_location = ALIGN(., 4);
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
link_bss_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
.stack : /* Contains the initial stack */
|
||||
{
|
||||
link_stack_location = ALIGN(., 4);
|
||||
*(.stack)
|
||||
. = ALIGN(MAX(link_stack_location + __STACKSIZE__ , .), 4);
|
||||
link_stack_end = .;
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.attributes*)
|
||||
*(.comment)
|
||||
*(.init)
|
||||
*(.preinit)
|
||||
*(.fini)
|
||||
*(.fini_array)
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
*(.v4_bx)
|
||||
*(.vfp11_veneer)
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.glue*)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Declare libc Heap to start at end of allocated RAM */
|
||||
|
||||
PROVIDE( _heap = link_stack_end );
|
||||
|
||||
/* End of the heap is top of RAM, aligned 8 byte */
|
||||
|
||||
PROVIDE( _eheap = ALIGN( ORIGIN( SRAM ) + LENGTH( SRAM ) - 8, 8 ) );
|
||||
|
||||
136
mico-os/platform/MCU/STM32F4xx/GCC/bootloader.ld
Normal file
136
mico-os/platform/MCU/STM32F4xx/GCC/bootloader.ld
Normal file
@@ -0,0 +1,136 @@
|
||||
/**
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
Reset_Handler = _start;
|
||||
|
||||
ENTRY( _start );
|
||||
|
||||
/* Include memory map */
|
||||
INCLUDE memory.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.ramcode_copy :
|
||||
{
|
||||
KEEP(*(*.interrupt_vector_table_copy_ramcode))
|
||||
KEEP(*(.copy_ramcode))
|
||||
. = ALIGN(512);
|
||||
}>BL_FLASH AT> BL_FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
|
||||
|
||||
link_run_from_ram_code_flash_location = LOADADDR( .text );
|
||||
link_run_from_ram_code_ram_location = .;
|
||||
link_interrupt_vectors_location = .;
|
||||
KEEP(*(*.interrupt_vector_table))
|
||||
KEEP(*(.stub_section))
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_code_location = .;
|
||||
KEEP(*(.text.irq ))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
link_code_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_const_variable_data_location = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
link_const_variable_data_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_constructors_location = .;
|
||||
KEEP(*(.preinit_array))
|
||||
KEEP(*(.init_array))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
link_constructors_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
|
||||
link_destructors_location = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
link_destructors_end = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
|
||||
link_run_from_ram_code_ram_end = .;
|
||||
|
||||
}>SRAM AT> BL_FLASH
|
||||
|
||||
|
||||
.data : /* Contains the non-zero initialised global variables */
|
||||
{
|
||||
link_global_data_initial_values = LOADADDR( .data ); /* This is the location in flash of the initial values of global variables */
|
||||
link_global_data_start = .;
|
||||
*(.data*)
|
||||
link_global_data_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}> SRAM AT> BL_FLASH
|
||||
|
||||
|
||||
.bss : /* Zero initialised memory used for zero initialised variables */
|
||||
{
|
||||
link_bss_location = ALIGN(., 4);
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
link_bss_end = .;
|
||||
. = ALIGN(., 4);
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
.stack : /* Contains the initial stack */
|
||||
{
|
||||
link_stack_location = ALIGN(., 4);
|
||||
*(.stack)
|
||||
. = ALIGN(MAX(link_stack_location + __STACKSIZE__ , .), 4);
|
||||
link_stack_end = .;
|
||||
}> SRAM AT> SRAM
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.attributes*)
|
||||
*(.comment)
|
||||
*(.init)
|
||||
*(.preinit)
|
||||
*(.fini)
|
||||
*(.fini_array)
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
*(.v4_bx)
|
||||
*(.vfp11_veneer)
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.glue*)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Declare libc Heap to start at end of allocated RAM */
|
||||
|
||||
PROVIDE( _heap = link_stack_end );
|
||||
|
||||
/* End of the heap is top of RAM, aligned 8 byte */
|
||||
|
||||
PROVIDE( _eheap = ALIGN( ORIGIN( SRAM ) + LENGTH( SRAM ) - 8, 8 ) );
|
||||
|
||||
166
mico-os/platform/MCU/STM32F4xx/GCC/platform_unhandled_isr.c
Normal file
166
mico-os/platform/MCU/STM32F4xx/GCC/platform_unhandled_isr.c
Normal file
@@ -0,0 +1,166 @@
|
||||
/**
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* Defines STM32F4xx default unhandled ISR and default mappings to unhandled ISR
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include "platform_assert.h"
|
||||
#include "platform_cmsis.h"
|
||||
#include "platform_isr.h"
|
||||
|
||||
/******************************************************
|
||||
* Macros
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Constants
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Enumerations
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Type Definitions
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Structures
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Static Function Declarations
|
||||
******************************************************/
|
||||
|
||||
extern void UnhandledInterrupt( void );
|
||||
|
||||
/******************************************************
|
||||
* Variable Definitions
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Function Definitions
|
||||
******************************************************/
|
||||
|
||||
PLATFORM_DEFINE_ISR( UnhandledInterrupt )
|
||||
{
|
||||
uint32_t active_interrupt_vector = (uint32_t) ( SCB->ICSR & 0x3fU );
|
||||
//
|
||||
// /* This variable tells you which interrupt vector is currently active */
|
||||
(void)active_interrupt_vector;
|
||||
// MICO_TRIGGER_BREAKPOINT( );
|
||||
|
||||
while( 1 )
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
* Default IRQ Handler Declarations
|
||||
******************************************************/
|
||||
|
||||
PLATFORM_SET_DEFAULT_ISR( NMI_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( HardFault_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( MemManage_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( BusFault_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( UsageFault_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SVC_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DebugMon_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( PendSV_Handler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( WWDG_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( PVD_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TAMP_STAMP_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( RTC_WKUP_irq , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FLASH_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( RCC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI0_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream0_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream6_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( ADC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN1_TX_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN1_RX0_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN1_RX1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN1_SCE_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI9_5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM1_BRK_TIM9_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM1_UP_TIM10_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM1_TRG_COM_TIM11_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM1_CC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C1_EV_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C1_ER_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C2_EV_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C2_ER_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SPI1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SPI2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( USART1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( USART2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( USART3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( EXTI15_10_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( RTC_Alarm_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_FS_WKUP_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM8_BRK_TIM12_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM8_UP_TIM13_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM8_TRG_COM_TIM14_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM8_CC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA1_Stream7_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FMC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FSMC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SDIO_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SPI3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( UART4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( UART5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM6_DAC_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( TIM7_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream0_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream2_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream3_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( ETH_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( ETH_WKUP_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN2_TX_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN2_RX0_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN2_RX1_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CAN2_SCE_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_FS_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream6_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DMA2_Stream7_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( USART6_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C3_EV_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( I2C3_ER_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_HS_EP1_OUT_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_HS_EP1_IN_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_HS_WKUP_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( OTG_HS_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( DCMI_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( CRYP_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( HASH_RNG_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FPU_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SPI4_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( SPI5_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( QUADSPI_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FMPI2C1_EV_IRQHandler , UnhandledInterrupt )
|
||||
PLATFORM_SET_DEFAULT_ISR( FMPI2C1_ER_IRQHandler , UnhandledInterrupt )
|
||||
|
||||
Reference in New Issue
Block a user