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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置

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OOP
2025-03-03 21:49:41 +08:00
parent e1e00b60ce
commit 9f9d4c7a56
4468 changed files with 1473046 additions and 10728 deletions
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34
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/ble_smtcn_app.h Normal file
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/* Copyright Statement:
*
* @2015 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek Inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE.
*/
void ble_smtcn_set_adv(void);

52
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/bt_init.h Normal file
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __BT_INIT_H__
#define __BT_INIT_H__
#ifdef __cplusplus
extern "C" {
#endif
void bt_init(void);
#ifdef __cplusplus
}
#endif
#endif //__BT_INIT_H__

55
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/bt_lwip.h Normal file
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __BT_LWIP_H__
#define __BT_LWIP_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined(MTK_BT_LWIP_ENABLE)
void bt_lwip_init(void);
void bt_lwip_send(const void *data, size_t size);
#endif
#ifdef __cplusplus
}
#endif
#endif // #ifndef __BT_LWIP_H__

21
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/cli_cmds.h Normal file
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#ifndef __CLI_CMDS_H__
#define __CLI_CMDS_H__
#if defined(MTK_MINICLI_ENABLE)
#include "cli.h"
#ifdef __cplusplus
extern "C" {
#endif
void cli_cmds_init(cli_t *cli);
#ifdef __cplusplus
}
#endif
#endif /* MTK_MINICLI_ENABLE */
#endif /* __CLI_CMDS_H__ */

58
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/cli_def.h Normal file
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __CLI_DEF_H__
#define __CLI_DEF_H__
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************
* API Functions
*****************************************************************************/
void cli_def_create(void);
void cli_def_task(void *param);
int cli_task_create(void);
#ifdef __cplusplus
}
#endif
#endif /* __CLI_DEF_H__ */

90
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/default_config.h Normal file
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __DEFAULT_CONFIG_H__
#define __DEFAULT_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
// start of wifi profile
#define DEF_WIFI_STA_MAC_ADDR "00:0C:43:76:87:28"
#define DEF_WIFI_AP_MAC_ADDR "00:0C:43:76:87:30"
#define DEF_WIFI_SSID "DontConnectMe2G"
#if 1
// open-none
#define DEF_WIFI_AUTH_MODE (0) //0:Ndis802_11AuthModeOpen, 7:Ndis802_11AuthModeWPA2PSK
#define DEF_WIFI_ENCRYPT_TYPE (1) //1: Ndis802_11EncryptionDisabled 5:Ndis802_11Encryption3Enabled
#else
// wpa2-psk
#define DEF_WIFI_AUTH_MODE (7) //0:Ndis802_11AuthModeOpen, 7:Ndis802_11AuthModeWPA2PSK
#define DEF_WIFI_ENCRYPT_TYPE (5) //1: Ndis802_11EncryptionDisabled 5:Ndis802_11Encryption3Enabled
#endif
#define DEF_WIFI_WIRELESS_MODE (9) //PHY_11BGN_MIXED, // if check 802.11b. 9
#define DEF_WIFI_CHANNEL (1)
#define DEF_WIFI_BSS_TYPE (1) //BSS_INFRA
#define DEF_WIFI_BW (0) //BW_20
#define DEF_WIFI_MCS (33) //MCS_AUTO
#define DEF_WIFI_COUNTRY_REGION (5) //REGION_5_BG_BAND
#define DEF_WIFI_COUNTRY_REGION_A_BAND (7) //REGION_7_A_BAND
#define DEF_WIFI_DBG_LEVEL (1) //RT_DEBUG_ERROR
// end of wifi profile
// start of system config
#define DEF_STA_IP_ADDR "192.168.0.28"
#define DEF_STA_IP_NETMASK "255.255.255.0"
#define DEF_STA_IP_GATEWAY "192.168.0.1"
#define DEF_AP_IP_ADDR "192.168.1.12"
#define DEF_AP_IP_NETMASK "255.255.255.0"
#define DEF_AP_IP_GATEWAY "192.168.1.254"
// end of system config
// start of wpa_supplicant config
#define DEF_SUPP_KEY_MGMT (0x100) // 0x100: WPA_KEY_MGMT_NONE, 0x10: WPA_KEY_MGMT_PSK
#define DEF_SUPP_SSID "DontConnectMe2G"
#define DEF_SUPP_PASSPHRASE "12345678"
// end of wpa_supplicant config
#ifdef __cplusplus
}
#endif
#endif // #ifndef __DEFAULT_CONFIG_H__

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mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/ept_eint_drv.h Normal file
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/*
* Generated by MTK Easy PinMux Tool Version 1.0.4 for 7687. Copyright MediaTek Inc. (C) 2015.
* Thu Jun 30 15:06:22 2016
* Do Not Modify the File.
*/
/*****************************************************************************
*
* Filename:
* ---------
* ***.*
*
* Project:
* --------
*
* Description:
* ------------
*
* Author:
* -------
*
*============================================================================
****************************************************************************/
#ifndef _EPT_EINT_DRV_H
#define _EPT_EINT_DRV_H
#endif /* _EPT_EINT_DRV_H */

650
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/ept_gpio_drv.h Normal file
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/*
* Generated by MTK Easy PinMux Tool Version 1.0.4 for 7687. Copyright MediaTek Inc. (C) 2015.
* Thu Jun 30 15:06:22 2016
* Do Not Modify the File.
*/
/*****************************************************************************
*
* Filename:
* ---------
* ***.*
*
* Project:
* --------
*
* Description:
* ------------
*
* Author:
* -------
*
*============================================================================
****************************************************************************/
#ifndef _EPT_GPIO_DRV_H
#define _EPT_GPIO_DRV_H
#define MODE_0 0
#define MODE_1 1
#define MODE_2 2
#define MODE_3 3
#define MODE_4 4
#define MODE_5 5
#define MODE_6 6
#define MODE_7 7
#define MODE_8 8
#define MODE_9 9
#define MODE_NC 0
#define OUTPUT_ENABLE 1
#define OUTPUT_DISABLE 0
#define IES_ENABLE 1
#define IES_DISABLE 0
#define PULL_UP_ENABLE 1
#define PULL_UP_DISABLE 0
#define PULL_DOWN_ENABLE 1
#define PULL_DOWN_DISABLE 0
#define GPIO_PORTNULL_MODE 0
#define GPIO_PORTNULL_OE 0
#define GPIO_PORTNULL_IES 0
#define GPIO_PORTNULL_PULL_UP 0
#define GPIO_PORTNULL_PULL_DOWN 0
#define GPIO_PORTNULL_OUTPUT 0
#define GPIO_PORT0_MODE MODE_7 // 7:UART1_RTS_CM4
#define GPIO_PORT1_MODE MODE_7 // 7:UART1_CTS_CM4
#define GPIO_PORT2_MODE MODE_7 // 7:UART1_RX_CM4
#define GPIO_PORT3_MODE MODE_7 // 7:UART1_TX_CM4
#define GPIO_PORT4_MODE MODE_7 // 7:SPI_DATA0_EXT
#define GPIO_PORT5_MODE MODE_7 // 7:SPI_DATA1_EXT
#define GPIO_PORT6_MODE MODE_8 // 8:GPIO6
#define GPIO_PORT7_MODE MODE_7 // 7:SPI_CS_EXT
#define GPIO_PORT8_MODE MODE_8 // 8:GPIO8
#define GPIO_PORT9_MODE MODE_8 // 8:GPIO9
#define GPIO_PORT10_MODE MODE_8 // 8:GPIO10
#define GPIO_PORT11_MODE MODE_8 // 8:GPIO11
#define GPIO_PORT12_MODE MODE_8 // 8:GPIO12
#define GPIO_PORT13_MODE MODE_8 // 8:GPIO13
#define GPIO_PORT14_MODE MODE_8 // 8:GPIO14
#define GPIO_PORT15_MODE MODE_8 // 8:GPIO15
#define GPIO_PORT16_MODE MODE_8 // 8:GPIO16
#define GPIO_PORT17_MODE MODE_8 // 8:GPIO17
#define GPIO_PORT18_MODE MODE_8 // 8:GPIO18
#define GPIO_PORT19_MODE MODE_8 // 8:GPIO19
#define GPIO_PORT20_MODE MODE_8 // 8:GPIO20
#define GPIO_PORT21_MODE MODE_8 // 8:GPIO21
#define GPIO_PORT22_MODE MODE_8 // 8:GPIO22
#define GPIO_PORT23_MODE MODE_8 // 8:GPIO23
#define GPIO_PORT24_MODE MODE_7 // 7:SPI_DATA2_EXT
#define GPIO_PORT25_MODE MODE_7 // 7:SPI_DATA3_EXT
#define GPIO_PORT26_MODE MODE_7 // 7:SPI_CLK_EXT
#define GPIO_PORT27_MODE MODE_4 // 4:I2C1_CLK
#define GPIO_PORT28_MODE MODE_4 // 4:I2C1_DATA
#define GPIO_PORT29_MODE MODE_8 // 8:GPIO29
#define GPIO_PORT30_MODE MODE_8 // 8:GPIO30
#define GPIO_PORT31_MODE MODE_8 // 8:GPIO31
#define GPIO_PORT32_MODE MODE_8 // 8:GPIO32
#define GPIO_PORT33_MODE MODE_8 // 8:GPIO33
#define GPIO_PORT34_MODE MODE_8 // 8:GPIO34
#define GPIO_PORT35_MODE MODE_NC
#define GPIO_PORT36_MODE MODE_7 // 7:UART2_RX_CM4
#define GPIO_PORT37_MODE MODE_7 // 7:UART2_TX_CM4
#define GPIO_PORT38_MODE MODE_8 // 8:GPIO38
#define GPIO_PORT39_MODE MODE_8 // 8:GPIO39
#define GPIO_PORT40_MODE MODE_8 // 8:GPIO40
#define GPIO_PORT41_MODE MODE_8 // 8:GPIO41
#define GPIO_PORT42_MODE MODE_8 // 8:GPIO42
#define GPIO_PORT43_MODE MODE_8 // 8:GPIO43
#define GPIO_PORT44_MODE MODE_8 // 8:GPIO44
#define GPIO_PORT45_MODE MODE_8 // 8:GPIO45
#define GPIO_PORT46_MODE MODE_8 // 8:GPIO46
#define GPIO_PORT47_MODE MODE_8 // 8:GPIO47
#define GPIO_PORT48_MODE MODE_8 // 8:GPIO48
#define GPIO_PORT49_MODE MODE_8 // 8:GPIO49
#define GPIO_PORT50_MODE MODE_8 // 8:GPIO50
#define GPIO_PORT51_MODE MODE_8 // 8:GPIO51
#define GPIO_PORT52_MODE MODE_8 // 8:GPIO52
#define GPIO_PORT53_MODE MODE_8 // 8:GPIO53
#define GPIO_PORT54_MODE MODE_8 // 8:GPIO54
#define GPIO_PORT55_MODE MODE_8 // 8:GPIO55
#define GPIO_PORT56_MODE MODE_8 // 8:GPIO56
#define GPIO_PORT57_MODE MODE_8 // 8:GPIO57
#define GPIO_PORT58_MODE MODE_8 // 8:GPIO58
#define GPIO_PORT59_MODE MODE_6 // 6:SWD_DIO
#define GPIO_PORT60_MODE MODE_6 // 6:SWD_CLK
#define GPIO_PORT61_MODE MODE_8 // 8:GPIO61
#define GPIO_PORT62_MODE MODE_8 // 8:GPIO62
#define GPIO_PORT63_MODE MODE_8 // 8:GPIO63
#define GPIO_PORT64_MODE MODE_8 // 8:GPIO64
#define GPIO_PORT65_MODE MODE_8 // 8:GPIO65
#define GPIO_PORT66_MODE MODE_8 // 8:GPIO66
#define GPIO_PORT67_MODE MODE_8 // 8:GPIO67
#define GPIO_PORT68_MODE MODE_8 // 8:GPIO68
#define GPIO_PORT69_MODE MODE_8 // 8:GPIO69
#define GPIO_PORT70_MODE MODE_8 // 8:GPIO70
#define GPIO_PORT71_MODE MODE_8 // 8:GPIO71
#define GPIO_PORT72_MODE MODE_8 // 8:GPIO72
// Input
#define GPIO_PORT0_OE OUTPUT_DISABLE
#define GPIO_PORT0_IES IES_ENABLE
// Input
#define GPIO_PORT1_OE OUTPUT_DISABLE
#define GPIO_PORT1_IES IES_ENABLE
// Input
#define GPIO_PORT2_OE OUTPUT_DISABLE
#define GPIO_PORT2_IES IES_ENABLE
// Input
#define GPIO_PORT3_OE OUTPUT_DISABLE
#define GPIO_PORT3_IES IES_ENABLE
// Input
#define GPIO_PORT4_OE OUTPUT_DISABLE
#define GPIO_PORT4_IES IES_ENABLE
// Input
#define GPIO_PORT5_OE OUTPUT_DISABLE
#define GPIO_PORT5_IES IES_ENABLE
// Output
#define GPIO_PORT6_OE OUTPUT_ENABLE
#define GPIO_PORT6_IES IES_DISABLE
// Input
#define GPIO_PORT7_OE OUTPUT_DISABLE
#define GPIO_PORT7_IES IES_ENABLE
// Input
#define GPIO_PORT8_OE OUTPUT_DISABLE
#define GPIO_PORT8_IES IES_ENABLE
// Input
#define GPIO_PORT9_OE OUTPUT_DISABLE
#define GPIO_PORT9_IES IES_ENABLE
// Input
#define GPIO_PORT10_OE OUTPUT_DISABLE
#define GPIO_PORT10_IES IES_ENABLE
// Input
#define GPIO_PORT11_OE OUTPUT_DISABLE
#define GPIO_PORT11_IES IES_ENABLE
// Input
#define GPIO_PORT12_OE OUTPUT_DISABLE
#define GPIO_PORT12_IES IES_ENABLE
// Input
#define GPIO_PORT13_OE OUTPUT_DISABLE
#define GPIO_PORT13_IES IES_ENABLE
// Input
#define GPIO_PORT14_OE OUTPUT_DISABLE
#define GPIO_PORT14_IES IES_ENABLE
// Input
#define GPIO_PORT15_OE OUTPUT_DISABLE
#define GPIO_PORT15_IES IES_ENABLE
// Input
#define GPIO_PORT16_OE OUTPUT_DISABLE
#define GPIO_PORT16_IES IES_ENABLE
// Input
#define GPIO_PORT17_OE OUTPUT_DISABLE
#define GPIO_PORT17_IES IES_ENABLE
// Input
#define GPIO_PORT18_OE OUTPUT_DISABLE
#define GPIO_PORT18_IES IES_ENABLE
// Input
#define GPIO_PORT19_OE OUTPUT_DISABLE
#define GPIO_PORT19_IES IES_ENABLE
// Input
#define GPIO_PORT20_OE OUTPUT_DISABLE
#define GPIO_PORT20_IES IES_ENABLE
// Input
#define GPIO_PORT21_OE OUTPUT_DISABLE
#define GPIO_PORT21_IES IES_ENABLE
// Input
#define GPIO_PORT22_OE OUTPUT_DISABLE
#define GPIO_PORT22_IES IES_ENABLE
// Input
#define GPIO_PORT23_OE OUTPUT_DISABLE
#define GPIO_PORT23_IES IES_ENABLE
// Input
#define GPIO_PORT24_OE OUTPUT_DISABLE
#define GPIO_PORT24_IES IES_ENABLE
// Input
#define GPIO_PORT25_OE OUTPUT_DISABLE
#define GPIO_PORT25_IES IES_ENABLE
// Input
#define GPIO_PORT26_OE OUTPUT_DISABLE
#define GPIO_PORT26_IES IES_ENABLE
// Input
#define GPIO_PORT27_OE OUTPUT_DISABLE
#define GPIO_PORT27_IES IES_ENABLE
// Input
#define GPIO_PORT28_OE OUTPUT_DISABLE
#define GPIO_PORT28_IES IES_ENABLE
// Output
#define GPIO_PORT29_OE OUTPUT_ENABLE
#define GPIO_PORT29_IES IES_DISABLE
// Output
#define GPIO_PORT30_OE OUTPUT_ENABLE
#define GPIO_PORT30_IES IES_DISABLE
// Output
#define GPIO_PORT31_OE OUTPUT_ENABLE
#define GPIO_PORT31_IES IES_DISABLE
// Output
#define GPIO_PORT32_OE OUTPUT_ENABLE
#define GPIO_PORT32_IES IES_DISABLE
// Output
#define GPIO_PORT33_OE OUTPUT_ENABLE
#define GPIO_PORT33_IES IES_DISABLE
// Output
#define GPIO_PORT34_OE OUTPUT_ENABLE
#define GPIO_PORT34_IES IES_DISABLE
// Input
#define GPIO_PORT35_OE OUTPUT_DISABLE
#define GPIO_PORT35_IES IES_ENABLE
// Input
#define GPIO_PORT36_OE OUTPUT_DISABLE
#define GPIO_PORT36_IES IES_ENABLE
// Input
#define GPIO_PORT37_OE OUTPUT_DISABLE
#define GPIO_PORT37_IES IES_ENABLE
// Output
#define GPIO_PORT38_OE OUTPUT_ENABLE
#define GPIO_PORT38_IES IES_DISABLE
// Output
#define GPIO_PORT39_OE OUTPUT_ENABLE
#define GPIO_PORT39_IES IES_DISABLE
// Input
#define GPIO_PORT40_OE OUTPUT_DISABLE
#define GPIO_PORT40_IES IES_ENABLE
// Input
#define GPIO_PORT41_OE OUTPUT_DISABLE
#define GPIO_PORT41_IES IES_ENABLE
// Input
#define GPIO_PORT42_OE OUTPUT_DISABLE
#define GPIO_PORT42_IES IES_ENABLE
// Input
#define GPIO_PORT43_OE OUTPUT_DISABLE
#define GPIO_PORT43_IES IES_ENABLE
// Input
#define GPIO_PORT44_OE OUTPUT_DISABLE
#define GPIO_PORT44_IES IES_ENABLE
// Input
#define GPIO_PORT45_OE OUTPUT_DISABLE
#define GPIO_PORT45_IES IES_ENABLE
// Input
#define GPIO_PORT46_OE OUTPUT_DISABLE
#define GPIO_PORT46_IES IES_ENABLE
// Input
#define GPIO_PORT47_OE OUTPUT_DISABLE
#define GPIO_PORT47_IES IES_ENABLE
// Input
#define GPIO_PORT48_OE OUTPUT_DISABLE
#define GPIO_PORT48_IES IES_ENABLE
// Input
#define GPIO_PORT49_OE OUTPUT_DISABLE
#define GPIO_PORT49_IES IES_ENABLE
// Input
#define GPIO_PORT50_OE OUTPUT_DISABLE
#define GPIO_PORT50_IES IES_ENABLE
// Input
#define GPIO_PORT51_OE OUTPUT_DISABLE
#define GPIO_PORT51_IES IES_ENABLE
// Input
#define GPIO_PORT52_OE OUTPUT_DISABLE
#define GPIO_PORT52_IES IES_ENABLE
// Input
#define GPIO_PORT53_OE OUTPUT_DISABLE
#define GPIO_PORT53_IES IES_ENABLE
// Input
#define GPIO_PORT54_OE OUTPUT_DISABLE
#define GPIO_PORT54_IES IES_ENABLE
// Input
#define GPIO_PORT55_OE OUTPUT_DISABLE
#define GPIO_PORT55_IES IES_ENABLE
// Input
#define GPIO_PORT56_OE OUTPUT_DISABLE
#define GPIO_PORT56_IES IES_ENABLE
// Output
#define GPIO_PORT57_OE OUTPUT_ENABLE
#define GPIO_PORT57_IES IES_DISABLE
// Output
#define GPIO_PORT58_OE OUTPUT_ENABLE
#define GPIO_PORT58_IES IES_DISABLE
// Input
#define GPIO_PORT59_OE OUTPUT_DISABLE
#define GPIO_PORT59_IES IES_ENABLE
// Input
#define GPIO_PORT60_OE OUTPUT_DISABLE
#define GPIO_PORT60_IES IES_ENABLE
// Input
#define GPIO_PORT61_OE OUTPUT_DISABLE
#define GPIO_PORT61_IES IES_ENABLE
// Input
#define GPIO_PORT62_OE OUTPUT_DISABLE
#define GPIO_PORT62_IES IES_ENABLE
// Input
#define GPIO_PORT63_OE OUTPUT_DISABLE
#define GPIO_PORT63_IES IES_ENABLE
// Input
#define GPIO_PORT64_OE OUTPUT_DISABLE
#define GPIO_PORT64_IES IES_ENABLE
// Input
#define GPIO_PORT65_OE OUTPUT_DISABLE
#define GPIO_PORT65_IES IES_ENABLE
// Input
#define GPIO_PORT66_OE OUTPUT_DISABLE
#define GPIO_PORT66_IES IES_ENABLE
// Input
#define GPIO_PORT67_OE OUTPUT_DISABLE
#define GPIO_PORT67_IES IES_ENABLE
// Input
#define GPIO_PORT68_OE OUTPUT_DISABLE
#define GPIO_PORT68_IES IES_ENABLE
// Input
#define GPIO_PORT69_OE OUTPUT_DISABLE
#define GPIO_PORT69_IES IES_ENABLE
// Input
#define GPIO_PORT70_OE OUTPUT_DISABLE
#define GPIO_PORT70_IES IES_ENABLE
// Input
#define GPIO_PORT71_OE OUTPUT_DISABLE
#define GPIO_PORT71_IES IES_ENABLE
// Input
#define GPIO_PORT72_OE OUTPUT_DISABLE
#define GPIO_PORT72_IES IES_ENABLE
#define GPIO_PORT0_OUTPUT 0
#define GPIO_PORT1_OUTPUT 0
#define GPIO_PORT2_OUTPUT 0
#define GPIO_PORT3_OUTPUT 0
#define GPIO_PORT4_OUTPUT 0
#define GPIO_PORT5_OUTPUT 0
#define GPIO_PORT6_OUTPUT 1
#define GPIO_PORT7_OUTPUT 0
#define GPIO_PORT8_OUTPUT 0
#define GPIO_PORT9_OUTPUT 0
#define GPIO_PORT10_OUTPUT 0
#define GPIO_PORT11_OUTPUT 0
#define GPIO_PORT12_OUTPUT 0
#define GPIO_PORT13_OUTPUT 0
#define GPIO_PORT14_OUTPUT 0
#define GPIO_PORT15_OUTPUT 0
#define GPIO_PORT16_OUTPUT 0
#define GPIO_PORT17_OUTPUT 0
#define GPIO_PORT18_OUTPUT 0
#define GPIO_PORT19_OUTPUT 0
#define GPIO_PORT20_OUTPUT 0
#define GPIO_PORT21_OUTPUT 0
#define GPIO_PORT22_OUTPUT 0
#define GPIO_PORT23_OUTPUT 0
#define GPIO_PORT24_OUTPUT 0
#define GPIO_PORT25_OUTPUT 0
#define GPIO_PORT26_OUTPUT 0
#define GPIO_PORT27_OUTPUT 0
#define GPIO_PORT28_OUTPUT 0
#define GPIO_PORT29_OUTPUT 0
#define GPIO_PORT30_OUTPUT 0
#define GPIO_PORT31_OUTPUT 0
#define GPIO_PORT32_OUTPUT 0
#define GPIO_PORT33_OUTPUT 0
#define GPIO_PORT34_OUTPUT 0
#define GPIO_PORT35_OUTPUT 0
#define GPIO_PORT36_OUTPUT 0
#define GPIO_PORT37_OUTPUT 0
#define GPIO_PORT38_OUTPUT 1
#define GPIO_PORT39_OUTPUT 0
#define GPIO_PORT40_OUTPUT 0
#define GPIO_PORT41_OUTPUT 0
#define GPIO_PORT42_OUTPUT 0
#define GPIO_PORT43_OUTPUT 0
#define GPIO_PORT44_OUTPUT 0
#define GPIO_PORT45_OUTPUT 0
#define GPIO_PORT46_OUTPUT 0
#define GPIO_PORT47_OUTPUT 0
#define GPIO_PORT48_OUTPUT 0
#define GPIO_PORT49_OUTPUT 0
#define GPIO_PORT50_OUTPUT 0
#define GPIO_PORT51_OUTPUT 0
#define GPIO_PORT52_OUTPUT 0
#define GPIO_PORT53_OUTPUT 0
#define GPIO_PORT54_OUTPUT 0
#define GPIO_PORT55_OUTPUT 0
#define GPIO_PORT56_OUTPUT 0
#define GPIO_PORT57_OUTPUT 0
#define GPIO_PORT58_OUTPUT 0
#define GPIO_PORT59_OUTPUT 0
#define GPIO_PORT60_OUTPUT 0
#define GPIO_PORT61_OUTPUT 0
#define GPIO_PORT62_OUTPUT 0
#define GPIO_PORT63_OUTPUT 0
#define GPIO_PORT64_OUTPUT 0
#define GPIO_PORT65_OUTPUT 0
#define GPIO_PORT66_OUTPUT 0
#define GPIO_PORT67_OUTPUT 0
#define GPIO_PORT68_OUTPUT 0
#define GPIO_PORT69_OUTPUT 0
#define GPIO_PORT70_OUTPUT 0
#define GPIO_PORT71_OUTPUT 0
#define GPIO_PORT72_OUTPUT 0
// Disable
#define GPIO_PORT0_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT0_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT1_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT1_PULL_DOWN PULL_DOWN_DISABLE
// Enable:_Pull_Up
#define GPIO_PORT2_PULL_UP PULL_UP_ENABLE
#define GPIO_PORT2_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT3_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT3_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT4_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT4_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT5_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT5_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT6_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT6_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT7_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT7_PULL_DOWN PULL_DOWN_DISABLE
// Enable:_Pull_Down
#define GPIO_PORT8_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT8_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT9_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT9_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT10_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT10_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT11_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT11_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT12_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT12_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT13_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT13_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT14_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT14_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT15_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT15_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT16_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT16_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT17_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT17_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT18_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT18_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT19_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT19_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT20_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT20_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT21_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT21_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT22_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT22_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT23_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT23_PULL_DOWN PULL_DOWN_ENABLE
// Disable
#define GPIO_PORT24_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT24_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT25_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT25_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT26_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT26_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT27_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT27_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT28_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT28_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT29_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT29_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT30_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT30_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT31_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT31_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT32_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT32_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT33_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT33_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT34_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT34_PULL_DOWN PULL_DOWN_DISABLE
// Enable:_Pull_Down
#define GPIO_PORT35_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT35_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Up
#define GPIO_PORT36_PULL_UP PULL_UP_ENABLE
#define GPIO_PORT36_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT37_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT37_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT38_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT38_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT39_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT39_PULL_DOWN PULL_DOWN_DISABLE
// Enable:_Pull_Down
#define GPIO_PORT40_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT40_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT41_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT41_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT42_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT42_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT43_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT43_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT44_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT44_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT45_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT45_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT46_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT46_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT47_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT47_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT48_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT48_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT49_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT49_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT50_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT50_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT51_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT51_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT52_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT52_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT53_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT53_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT54_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT54_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT55_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT55_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT56_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT56_PULL_DOWN PULL_DOWN_ENABLE
// Disable
#define GPIO_PORT57_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT57_PULL_DOWN PULL_DOWN_DISABLE
// Disable
#define GPIO_PORT58_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT58_PULL_DOWN PULL_DOWN_DISABLE
// Enable:_Pull_Down
#define GPIO_PORT59_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT59_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT60_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT60_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT61_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT61_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT62_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT62_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT63_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT63_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT64_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT64_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT65_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT65_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT66_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT66_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT67_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT67_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT68_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT68_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT69_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT69_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT70_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT70_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT71_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT71_PULL_DOWN PULL_DOWN_ENABLE
// Enable:_Pull_Down
#define GPIO_PORT72_PULL_UP PULL_UP_DISABLE
#define GPIO_PORT72_PULL_DOWN PULL_DOWN_ENABLE
#endif /* _EPT_GPIO_DRV_H */

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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __FLASH_MAP_H__
#define __FLASH_MAP_H__
#define FLASH_LOADER_SIZE 0x8000 /* 32KB */
#define FLASH_COMM_CONF_SIZE 0x0000 /* 0KB, dummy for 97 restore default build */
#define FLASH_STA_CONF_SIZE 0x0000 /* 0KB, dummy for 97 restore default build */
#define FLASH_AP_CONF_SIZE 0x0000 /* 0KB, dummy for 97 restore default build */
#define FLASH_N9_RAM_CODE_SIZE 0x71000 /* 452KB */
#define FLASH_CM4_XIP_CODE_SIZE 0x1ED000 /* 1972KB */
#define FLASH_TMP_SIZE 0x18A000 /* 1576KB */
#define FLASH_USR_CONF_SIZE 0x10000 /* 64KB */
#define CM4_FLASH_LOADER_ADDR 0x0
#define CM4_FLASH_COMM_CONF_ADDR (CM4_FLASH_LOADER_ADDR + FLASH_LOADER_SIZE) /* dummy for 97 restore default build */
#define CM4_FLASH_N9_RAMCODE_ADDR (CM4_FLASH_LOADER_ADDR + FLASH_LOADER_SIZE)
#define CM4_FLASH_CM4_ADDR (CM4_FLASH_N9_RAMCODE_ADDR + FLASH_N9_RAM_CODE_SIZE)
#define CM4_FLASH_TMP_ADDR (CM4_FLASH_CM4_ADDR + FLASH_CM4_XIP_CODE_SIZE)
#define CM4_FLASH_USR_CONF_ADDR (CM4_FLASH_TMP_ADDR + FLASH_TMP_SIZE)
#endif // __FLASH_MAP_H__

85
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __HAL_FEATURE_CONFIG_H__
#define __HAL_FEATURE_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************
* module ON or OFF feature option,only option in this temple
*****************************************************************************/
#define HAL_ADC_MODULE_ENABLED
#define HAL_AES_MODULE_ENABLED
#define HAL_CACHE_MODULE_ENABLED
#define HAL_DES_MODULE_ENABLED
#define HAL_EINT_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GDMA_MODULE_ENABLED
#define HAL_GPC_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_GPT_MODULE_ENABLED
#define HAL_I2C_MASTER_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRRX_MODULE_ENABLED
#define HAL_IRTX_MODULE_ENABLED
#define HAL_MD5_MODULE_ENABLED
#define HAL_NVIC_MODULE_ENABLED
#define HAL_PWM_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SHA_MODULE_ENABLED
#define HAL_SPI_MASTER_MODULE_ENABLED
#define HAL_SPI_SLAVE_MODULE_ENABLED
#define HAL_TRNG_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_WDT_MODULE_ENABLED
#define HAL_SLEEP_MANAGER_ENABLED
/*****************************************************************************
* * customization module feature option
* *****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HAL_FEATURE_CONFIG_H__ */

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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
/**
* @file hci_log.h
*
* HCI log out related function.
*
*/
#ifndef __HCI_LOG_H__
#define __HCI_LOG_H__
#include "stdint.h"
typedef enum {
HCI_COMMAND = 1,
HCI_EVENT = 2,
HCI_ACL_IN = 4,
HCI_ACL_OUT = 8,
} ENUM_HCI_DATA_TYPE;
/**
* @brief record HCI command.
*
* @param buf [IN] HCI command data.
* @param length [IN] indicate length of buf.
*
* @return size of buf had recorded, <0 means fail.
*
*/
int32_t hci_log_cmd(unsigned char *buf, int32_t length);
/**
* @brief record HCI event.
*
* @param buf [IN] HCI event data.
* @param length [IN] indicate length of buf.
*
* @return size of buf had recorded, <0 means fail.
*
*/
int32_t hci_log_event(unsigned char *buf, int32_t length);
/**
* @brief record HCI ACL data out.
*
* @param buf [IN] HCI ACL data out.
* @param length [IN] indicate length of buf.
*
* @return size of buf had recorded, <0 means fail.
*
*/
int32_t hci_log_acl_out(unsigned char *buf, int32_t length);
/**
* @brief record HCI ACL data in.
*
* @param buf [IN] HCI ACL data in.
* @param length [IN] indicate length of buf.
*
* @return size of buf had recorded, <0 means fail.
*
*/
int32_t hci_log_acl_in(unsigned char *buf, int32_t length);
#endif

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/*
* Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#include "FreeRTOSConfig.h"
#define LWIP_TCPIP_TIMEOUT 1
#define TCPIP_MBOX_SIZE 16
#define DEFAULT_RAW_RECVMBOX_SIZE 16
#define DEFAULT_UDP_RECVMBOX_SIZE 16
#define DEFAULT_TCP_RECVMBOX_SIZE 16
#define DEFAULT_ACCEPTMBOX_SIZE 16
//fix http IOT issue
#define LWIP_WND_SCALE 1
#define TCP_RCV_SCALE 1
#define MEMP_NUM_NETDB 4
//fix reuse address issue
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
//for ip display
#define LWIP_NETIF_STATUS_CALLBACK 1
#if defined(MTK_HOMEKIT_ENABLE)
#define LWIP_IPV6 1
#define IP_REASS_MAXAGE 60 // 3
#define LWIP_IPV6_FRAG 1
#define LWIP_MULTICAST_PING 1
#define LWIP_HAVE_LOOPIF 1
#define LWIP_IGMP 1
#define LWIP_NETIF_HOSTNAME 1
#define LWIP_DHCP_AUTOIP_COOP 1
#define LWIP_DHCP_AUTOIP_COOP_TRIES 3
#define LWIP_NETBUF_RECVINFO 1
#define LWIP_DNS 1
#define LWIP_SOCKET 1
#define LWIP_COMPAT_SOCKETS 1
#define LWIP_POSIX_SOCKETS_IO_NAMES 1
#define MEMP_NUM_NETBUF 16
#define MEMP_NUM_MLD6_GROUP 10
#define MEMP_NUM_ND6_QUEUE 30
#define LWIP_ND6_RETRANS_TIMER 200
#endif
#define ETH_PAD_SIZE 0
#define LWIP_IGMP 1
#define LWIP_DNS 1
#define LWIP_SOCKET 1
#define LWIP_COMPAT_SOCKETS 0
#define NO_SYS 0
#define LWIP_CALLBACK_API 1
/*
------------------------------------
---------- Memory options ----------
------------------------------------
*/
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
#define MEM_ALIGNMENT 4
/**
* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
* speed and usage from interrupts!
*/
#define MEMP_MEM_MALLOC 1
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
#if defined(MTK_WIFI_TGN_VERIFY_ENABLE) && !defined(MTK_HOMEKIT_ENABLE)
#define MEM_SIZE (100 * 1024)
#else
#define MEM_SIZE (36 * 1024)
#endif
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 1
/*
------------------------------------------------
---------- Internal Memory Pool Sizes ----------
------------------------------------------------
*/
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
#define MEMP_NUM_PBUF 8
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 8
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 32 //8 original
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
#define MEMP_NUM_TCP_PCB_LISTEN 32 //16 original
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
#define MEMP_NUM_TCP_SEG 255
/**
* MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
* packets (pbufs) that are waiting for an ARP request (to resolve
* their destination address) to finish.
* (requires the ARP_QUEUEING option)
*/
#define MEMP_NUM_ARP_QUEUE 8
/**
* MEMP_NUM_NETCONN: the number of struct netconns.
* (only needed if you use the sequential API, like api_lib.c)
*/
#define MEMP_NUM_NETCONN 18
/*
----------------------------------
---------- Pbuf options ----------
----------------------------------
*/
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
#define PBUF_POOL_SIZE 10
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
//#define PBUF_POOL_BUFSIZE 1536
/* packet of MT7687 IOT has extra TXD header and packet offset */
#define PBUF_POOL_BUFSIZE 1664
/**
* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
* link level header. The default is 14, the standard value for
* Ethernet.
*/
#define RESERVED_HLEN 0 //depend on CFG_CONNSYS_TXD_PAD_SIZE
#ifdef MTK_HIF_GDMA_ENABLE
#define PBUF_LINK_ENCAPSULATION_HLEN 2 // for WiFi headroom (TX zero copy)
#else
#define PBUF_LINK_ENCAPSULATION_HLEN 0
#endif
#define PBUF_LINK_HLEN (RESERVED_HLEN + 14 + ETH_PAD_SIZE)
/*
---------------------------------
---------- TCP options ----------
---------------------------------
*/
#define LWIP_TCP 1
#define TCP_TTL 255
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
#define TCP_QUEUE_OOSEQ 1
/* TCP Maximum segment size. */
#define TCP_MSS 1476
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (24 * 1024) //(12 * 1024)
/* TCP sender buffer space (pbufs). This must be at least = 2 *
TCP_SND_BUF/TCP_MSS for things to work. */
#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
/* TCP receive window. */
#define TCP_WND (24 * 1024)
/* Maximum number of retransmissions of data segments. */
#define TCP_MAXRTX 12
/* Maximum number of retransmissions of SYN segments. */
#define TCP_SYNMAXRTX 4
#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
/*
---------------------------------
---------- ARP options ----------
---------------------------------
*/
#define LWIP_ARP 1
#define ARP_TABLE_SIZE 10
#define ARP_QUEUEING 1
/* ---------- IP options ---------- */
/* Define IP_FORWARD to 1 if you wish to have the ability to forward
IP packets across network interfaces. If you are going to run lwIP
on a device with only one network interface, define this to 0. */
#define IP_FORWARD 0
/* If defined to 1, IP options are allowed (but not parsed). If
defined to 0, all packets with IP options are dropped. */
#define IP_OPTIONS 1
#define IP_REASSEMBLY 1
/**
* IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
* Since the received pbufs are enqueued, be sure to configure
* PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
* packets even if the maximum amount of fragments is enqueued for reassembly!
*/
#if defined(MTK_WIFI_TGN_VERIFY_ENABLE)
#define IP_REASS_MAX_PBUFS 25
#else
#define IP_REASS_MAX_PBUFS 10
#endif
/* ---------- ICMP options ---------- */
#define ICMP_TTL 255
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
#define LWIP_DHCP_CHECK_LINK_UP 1
/* 1 if you want to do an ARP check on the offered address
(recommended). */
#define DHCP_DOES_ARP_CHECK 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- Statistics options ---------- */
#if defined(MTK_LWIP_STATISTICS_ENABLE)
#define LWIP_STATS 1
#define LWIP_STATS_DISPLAY 1
#endif
/*
* Should use the default value defined in tcp_impl.h
*/
#if 0
/* -------- TCP Timer Intervals ------- */
#define TCP_TMR_INTERVAL 1 /* The TCP timer interval in
milliseconds. */
#define TCP_FAST_INTERVAL 2 /* the fine grained timeout in
milliseconds */
#define TCP_SLOW_INTERVAL 5 /* the coarse grained timeout in
milliseconds */
#endif
/*
------------------------------------
---------- AUTOIP options ----------
------------------------------------
*/
#if defined(MTK_HOMEKIT_ENABLE)
#define LWIP_AUTOIP 1
#else
#define LWIP_AUTOIP 0
#endif
/*
----------------------------------
---------- DNS options -----------
----------------------------------
*/
#define LWIP_DNS 1
/*
---------------------------------
---------- PPP options ----------
---------------------------------
*/
#define PPP_SUPPORT 0
/*
------------------------------------------------
---------- Network Interfaces options ----------
------------------------------------------------
*/
/**
* LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
* address equal to the netif IP address, looping them back up the stack.
*/
#define LWIP_NETIF_LOOPBACK 1
/**
* LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
* sending for each netif (0 = disabled)
*/
#define LWIP_LOOPBACK_MAX_PBUFS 12
/*
------------------------------------
---------- LOOPIF options ----------
------------------------------------
*/
/**
* LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
*/
#define LWIP_HAVE_LOOPIF 1
/*
* Should use the default value defined in opt.h
*/
#if 0
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0))
#endif
#if defined(MTK_LWIP_DYNAMIC_DEBUG_ENABLE)
struct lwip_debug_flags {
char *debug_flag_name;
uint32_t debug_flag;
};
extern struct lwip_debug_flags lwip_debug_flags[];
#define LWIP_DEBUG LWIP_DBG_ON
#define LWIP_DEBUG_IDX(idx) ((idx) >> 8)
#undef ETHARP_DEBUG
#undef NETIF_DEBUG
#undef PBUF_DEBUG
#undef API_LIB_DEBUG
#undef API_MSG_DEBUG
#undef SOCKETS_DEBUG
#undef ICMP_DEBUG
#undef IGMP_DEBUG
#undef INET_DEBUG
#undef IP_DEBUG
#undef IP_REASS_DEBUG
#undef RAW_DEBUG
#undef MEM_DEBUG
#undef MEMP_DEBUG
#undef SYS_DEBUG
#undef TIMERS_DEBUG
#undef TCP_DEBUG
#undef TCP_INPUT_DEBUG
#undef TCP_FR_DEBUG
#undef TCP_RTO_DEBUG
#undef TCP_CWND_DEBUG
#undef TCP_WND_DEBUG
#undef TCP_OUTPUT_DEBUG
#undef TCP_RST_DEBUG
#undef TCP_QLEN_DEBUG
#undef UDP_DEBUG
#undef TCPIP_DEBUG
#undef PPP_DEBUG
#undef SLIP_DEBUG
#undef DHCP_DEBUG
#undef AUTOIP_DEBUG
#undef SNMP_MSG_DEBUG
#undef SNMP_MIB_DEBUG
#undef DNS_DEBUG
#define ETHARP_DEBUG 0x0000U
#define NETIF_DEBUG 0x0100U
#define PBUF_DEBUG 0x0200U
#define API_LIB_DEBUG 0x0300U
#define API_MSG_DEBUG 0x0400U
#define SOCKETS_DEBUG 0x0500U
#define ICMP_DEBUG 0x0600U
#define IGMP_DEBUG 0x0700U
#define INET_DEBUG 0x0800U
#define IP_DEBUG 0x0900U
#define IP_REASS_DEBUG 0x0a00U
#define RAW_DEBUG 0x0b00U
#define MEM_DEBUG 0x0c00U
#define MEMP_DEBUG 0x0d00U
#define SYS_DEBUG 0x0e00U
#define TIMERS_DEBUG 0x0f00U
#define TCP_DEBUG 0x1000U
#define TCP_INPUT_DEBUG 0x1100U
#define TCP_FR_DEBUG 0x1200U
#define TCP_RTO_DEBUG 0x1300U
#define TCP_CWND_DEBUG 0x1400U
#define TCP_WND_DEBUG 0x1500U
#define TCP_OUTPUT_DEBUG 0x1600U
#define TCP_RST_DEBUG 0x1700U
#define TCP_QLEN_DEBUG 0x1800U
#define UDP_DEBUG 0x1900U
#define TCPIP_DEBUG 0x1a00U
#define PPP_DEBUG 0x1b00U
#define SLIP_DEBUG 0x1c00U
#define DHCP_DEBUG 0x1d00U
#define AUTOIP_DEBUG 0x1e00U
#define SNMP_MSG_DEBUG 0x1f00U
#define SNMP_MIB_DEBUG 0x2000U
#define DNS_DEBUG 0x2100U
#endif
// #define LWIP_DEBUG LWIP_DBG_ON
// #define ETHARP_DEBUG LWIP_DBG_ON
// #define NETIF_DEBUG LWIP_DBG_ON
// #define PBUF_DEBUG LWIP_DBG_ON
// #define API_LIB_DEBUG LWIP_DBG_ON
// #define API_MSG_DEBUG LWIP_DBG_ON
// #define SOCKETS_DEBUG LWIP_DBG_ON
// #define ICMP_DEBUG LWIP_DBG_ON
// #define IGMP_DEBUG LWIP_DBG_ON
// #define INET_DEBUG LWIP_DBG_ON
// #define IP_DEBUG LWIP_DBG_ON
// #define IP_REASS_DEBUG LWIP_DBG_ON
// #define RAW_DEBUG LWIP_DBG_ON
// #define MEM_DEBUG LWIP_DBG_ON
// #define MEMP_DEBUG LWIP_DBG_ON
// #define SYS_DEBUG LWIP_DBG_ON
// #define TIMERS_DEBUG LWIP_DBG_ON
// #define TCP_DEBUG LWIP_DBG_ON
// #define TCP_INPUT_DEBUG LWIP_DBG_ON
// #define TCP_FR_DEBUG LWIP_DBG_ON
// #define TCP_RTO_DEBUG LWIP_DBG_ON
// #define TCP_CWND_DEBUG LWIP_DBG_ON
// #define TCP_WND_DEBUG LWIP_DBG_ON
// #define TCP_OUTPUT_DEBUG LWIP_DBG_ON
// #define TCP_RST_DEBUG LWIP_DBG_ON
// #define TCP_QLEN_DEBUG LWIP_DBG_ON
// #define UDP_DEBUG LWIP_DBG_ON
// #define TCPIP_DEBUG LWIP_DBG_ON
// #define PPP_DEBUG LWIP_DBG_ON
// #define SLIP_DEBUG LWIP_DBG_ON
// #define DHCP_DEBUG LWIP_DBG_ON
// #define AUTOIP_DEBUG LWIP_DBG_ON
// #define SNMP_MSG_DEBUG LWIP_DBG_ON
// #define SNMP_MIB_DEBUG LWIP_DBG_ON
// #define DNS_DEBUG LWIP_DBG_ON
#endif /* __LWIPOPTS_H__ */

47
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#ifndef __MXCHIP_DEBUG_H__
#define __MXCHIP_DEBUG_H__
typedef int (*debug_printf)( char*msg, ... );
enum {
SYSTEM_DEBUG_NONE = 0,
SYSTEM_DEBUG_ERROR = 1,
SYSTEM_DEBUG_DEBUG = 2,
SYSTEM_DEBUG_INFO = 3,
};
extern debug_printf pPrintffunc;
extern int debug_level;
#if 0
#define system_debug_printf(level, ...) \
do {\
if ((level <= debug_level) && (pPrintffunc != NULL))\
pPrintffunc(__VA_ARGS__);\
}while(0)
#else
#include "syslog.h"
#define system_debug_printf(level, ...) \
do {\
extern uint8_t debug_enable;\
if(debug_enable){\
LOG_E(common, __VA_ARGS__);\
}\
} while(0)
#endif
#define cmd_printf(...) do{\
if (xWriteBufferLen > 0) {\
snprintf(pcWriteBuffer, xWriteBufferLen, __VA_ARGS__);\
xWriteBufferLen-=strlen(pcWriteBuffer);\
pcWriteBuffer+=strlen(pcWriteBuffer);\
}\
}while(0)
void system_debug_enable(int level, debug_printf callback);
#endif

45
mico-os/platform/MCU/MTK7697/apps/mxchipWnet/inc/project_config.h Normal file
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
/* max supported connection number */
#define BT_CONNECTION_MAX 16
/* max timer count */
#define BT_TIMER_NUM 10
#define BT_TX_BUF_SIZE 256
#define BT_RX_BUF_SIZE 1024
#define BT_TIMER_BUF_SIZE (BT_TIMER_NUM * BT_CONTROL_BLOCK_SIZE_OF_TIMER)
#define BT_CONNECTION_BUF_SIZE (BT_CONNECTION_MAX* BT_CONTROL_BLOCK_SIZE_OF_LE_CONNECTION)

52
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/* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#ifndef __NET_INIT_H__
#define __NET_INIT_H__
#ifdef __cplusplus
extern "C" {
#endif
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif //__NET_INIT_H__