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https://github.com/oopuuu/zTC1.git
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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
This commit is contained in:
OOP
441
mico-os/platform/MCU/LPC5410x/wlan_bus_driver/wlan_bus_SPI.c
Normal file
441
mico-os/platform/MCU/LPC5410x/wlan_bus_driver/wlan_bus_SPI.c
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@@ -0,0 +1,441 @@
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/**
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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*
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*/
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#include "mico_rtos.h"
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//#include "misc.h"
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#include "string.h" /* For memcpy */
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#include "platform_config.h"
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#include "platform_peripheral.h"
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#include "platform_logging.h"
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#include "wlan_platform_common.h"
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#include "chip.h"
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#define DMACHN_WLAN_RX DMAREQ_SPI1_RX
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#define DMACHN_WLAN_TX DMAREQ_SPI1_TX
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#define WLAN_SPI_BUS_MHZ 48
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#define WLAN_SPI_CLKCTL_BIT 10
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#define USE_WLAN_SPI_SEM
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// Caution: If USE_LINKED_DMA_XFER is enabled, DMA is configured to automatically
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// load next desc, this enforce some hard real-time requirements to the system!
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// It assumes user MUST finsih processing current desc transfer complete IRQ
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// before next desc transfer completes, otherwise, you will miss one IRQ!
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// Usually this is happened when the last desc has very small data size (E.g., 1 byte)
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// #define USE_LINKED_DMA_XFER
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// Magicoe TODO delete those tow parameter
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volatile uint8_t bDMASPITXDoneFlag = false;
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volatile uint8_t bDMASPIRXDoneFlag = false;
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#define SEMDELAY 200
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/******************************************************
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* Constants
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******************************************************/
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#define DMA_TIMEOUT_LOOPS (10000000)
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/**
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* Transfer direction for the mico platform bus interface
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*/
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typedef enum
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{
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/* If updating this enum, the bus_direction_mapping variable will also need to be updated */
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BUS_READ,
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BUS_WRITE
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} bus_transfer_direction_t;
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/******************************************************
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* Structures
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******************************************************/
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/******************************************************
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* Variables
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******************************************************/
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static mico_semaphore_t spi_transfer_finished_semaphore;
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/******************************************************
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* Function declarations
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******************************************************/
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/* Powersave functionality */
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extern void MCU_CLOCKS_NEEDED( void );
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extern void MCU_CLOCKS_NOT_NEEDED( void );
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extern void wlan_notify_irq( void );
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/******************************************************
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* Function definitions
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******************************************************/
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void spi_irq_handler( void* arg )
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{
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UNUSED_PARAMETER(arg);
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#ifndef MICO_DISABLE_MCU_POWERSAVE
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platform_mcu_powersave_exit_notify( );
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#endif
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wlan_notify_irq( );
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}
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typedef struct _DS_DualBufDMA
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{
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DMA_CHDESC_T *pRxDescs[1], *pTxDescs[1];
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uint8_t isToRx;
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uint8_t tglBit;
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uint8_t descPnding;
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uint32_t c1Rem; // bytes remain
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const uint8_t *pC1TxBuf;
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uint8_t *pC1RxBuf;
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}DS_DualBufDMA;
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volatile DS_DualBufDMA s_dbDMA;
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int32_t _prvDbDescCfgNext(void)
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{
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uint32_t tgl = s_dbDMA.tglBit;
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DMA_CHDESC_T *pTxDesc = s_dbDMA.pTxDescs[tgl];
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DMA_CHDESC_T *pRxDesc = s_dbDMA.pRxDescs[tgl];
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uint32_t xferLen = DMA_MAX_XFER_CNT;
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if (s_dbDMA.c1Rem == 0)
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return -1L;
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s_dbDMA.descPnding++;
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if (s_dbDMA.c1Rem <= DMA_MAX_XFER_CNT) {
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xferLen = s_dbDMA.c1Rem ;
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pRxDesc->next = pTxDesc->next = 0;
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} else {
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xferLen = DMA_MAX_XFER_CNT;
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pRxDesc->next = DMA_ADDR(s_dbDMA.pRxDescs[!tgl]);
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pTxDesc->next = DMA_ADDR(s_dbDMA.pTxDescs[!tgl]);
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}
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pTxDesc->source = DMA_ADDR(s_dbDMA.pC1TxBuf) + xferLen - 1;
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pTxDesc->xfercfg = DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA |
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DMA_XFERCFG_SWTRIG | DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 |
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DMA_XFERCFG_DSTINC_0 | DMA_XFERCFG_XFERCOUNT(xferLen);
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pRxDesc->dest = DMA_ADDR(s_dbDMA.pC1RxBuf) + xferLen - 1;
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pRxDesc->xfercfg = DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA |
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DMA_XFERCFG_SWTRIG | DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_DSTINC_1 |
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DMA_XFERCFG_SRCINC_0 | DMA_XFERCFG_XFERCOUNT(xferLen);
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s_dbDMA.c1Rem -= xferLen , s_dbDMA.pC1RxBuf += xferLen , s_dbDMA.pC1TxBuf += xferLen;
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return s_dbDMA.c1Rem;
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}
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void wlan_spi_xfer_done(uint32_t isRx)
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{
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/* Clear interrupt */
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// process only if the primary channel generates the IRQ, for SPI RX.
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if (--s_dbDMA.descPnding == 0 && s_dbDMA.c1Rem == 0) {
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#ifdef USE_WLAN_SPI_SEM
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#ifndef NO_MICO_RTOS
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mico_rtos_set_semaphore( &spi_transfer_finished_semaphore );
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#endif
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#else
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bDMASPITXDoneFlag = 1;
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bDMASPIRXDoneFlag = 1;
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#endif
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} else {
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// continue xfer
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// configure next desc
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_prvDbDescCfgNext();
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{
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DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) g_pDMA->SRAMBASE;
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// pDesc[DMACHN_WLAN_RX] = s_rxDescs[0];
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// pDesc[DMACHN_WLAN_TX] = s_txDescs[0];
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// rocky: only start DMA RX if it is for bus read
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// rocky: Toggle bit is not used if no linked DMA xfer
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if (s_dbDMA.isToRx)
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g_pDMA->DMACH[DMACHN_WLAN_RX].XFERCFG = pDesc[DMACHN_WLAN_RX].xfercfg;
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// rocky: DMA TX is ALWAYS initiated
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g_pDMA->DMACH[DMACHN_WLAN_TX].XFERCFG = pDesc[DMACHN_WLAN_TX].xfercfg;
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}
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}
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}
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void SpiLongXferTest(void);
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OSStatus host_platform_bus_init( void )
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{
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uint32_t pinCfg;
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platform_mcu_powersave_disable();
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pinCfg = IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
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if (WLAN_SPI_BUS_MHZ >= 24)
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pinCfg |= 1UL<<9; // enable fast slew
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g_pIO->PIO[1][6] = IOCON_FUNC2 | pinCfg;/* SPI1_SCK */
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g_pIO->PIO[1][7] = IOCON_FUNC2 | pinCfg; /* SPI1_MISO */
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g_pIO->PIO[1][8] = IOCON_FUNC2 | pinCfg; /* SPI1_MOSI */
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g_pIO->PIO[wifi_spi_pins[WIFI_PIN_SPI_CS].port][wifi_spi_pins[WIFI_PIN_SPI_CS].pin_number] = IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF; /* SPI1_SSEL0 */
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g_pGP->SET[wifi_spi_pins[WIFI_PIN_SPI_CS].port] = (uint32_t)(1ul<<(wifi_spi_pins[WIFI_PIN_SPI_CS].pin_number));// << 9;
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g_pGP->DIR[wifi_spi_pins[WIFI_PIN_SPI_CS].port] |= (uint32_t)(1ul<<(wifi_spi_pins[WIFI_PIN_SPI_CS].pin_number));// << 9;
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#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
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/* Set GPIO_B[1:0] to 01 to put WLAN module into gSPI mode */
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platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], OUTPUT_PUSH_PULL );
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platform_gpio_output_high( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0] );
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platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], OUTPUT_PUSH_PULL );
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platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1] );
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#endif
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// initialize SPI for Wlan
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{
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LPC_SPI_T *pSPI = LPC_SPI1;
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g_pASys->ASYNCAPBCLKCTRLSET = 1UL << 10; // enable clock to SPI1
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g_pASys->ASYNCPRESETCTRLSET = 1UL << 10;
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g_pASys->ASYNCPRESETCTRLCLR = 1UL << 10;
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// predly | postDly| fraDly | xferDly
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pSPI->DLY = 1UL<<0 | 1UL<<4 | 1UL<<8 | 1UL<<12;
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{
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uint32_t busClk = Chip_Clock_GetAsyncSyscon_ClockRate();
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uint32_t div = (busClk + WLAN_SPI_BUS_MHZ*1000000 - 1) / (WLAN_SPI_BUS_MHZ*1000000);
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pSPI->DIV = div - 1; // proper division
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}
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pSPI->TXCTRL = (8-1)<<24; // 8 bits per frame
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// Enable | master | MSBfirst | mode 3 | no loopback
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pSPI->CFG = 1UL<<0 | 1UL<<2 | 0UL<<3 | 3UL<<4 | 0UL<<7;
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}
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bDMASPITXDoneFlag = bDMASPIRXDoneFlag = false;
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/* Setup DMA for SPIX RX */
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g_pDMA->DMACOMMON[0].ENABLESET = (1UL<<DMACHN_WLAN_RX) | (1UL<<DMACHN_WLAN_TX);
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g_pDMA->DMACOMMON[0].INTENSET = (1UL<<DMACHN_WLAN_RX) | (1UL<<DMACHN_WLAN_TX);
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g_pDMA->DMACH[DMACHN_WLAN_RX].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(0);
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g_pDMA->DMACH[DMACHN_WLAN_TX].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(0);
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#ifndef NO_MICO_RTOS
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mico_rtos_init_semaphore(&spi_transfer_finished_semaphore, 1);
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#endif
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// setup PinINT for WLAN
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platform_gpio_init(wifi_spi_pins + WIFI_PIN_SPI_IRQ, INPUT_HIGH_IMPEDANCE);
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platform_gpio_irq_enable(wifi_spi_pins + WIFI_PIN_SPI_IRQ, IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, 0);
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platform_mcu_powersave_enable();
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SpiLongXferTest();
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return kNoErr;
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}
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OSStatus host_platform_bus_deinit( void )
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{
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platform_mcu_powersave_disable();
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#ifndef NO_MICO_RTOS
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mico_rtos_deinit_semaphore(&spi_transfer_finished_semaphore);
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#endif
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#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
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/* Clear GPIO_B[1:0] */
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platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], INPUT_HIGH_IMPEDANCE );
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platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], INPUT_HIGH_IMPEDANCE );
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#endif
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platform_gpio_irq_disable(wifi_spi_pins + WIFI_PIN_SPI_IRQ);
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g_pASys->ASYNCAPBCLKCTRLCLR = 1UL<<WLAN_SPI_CLKCTL_BIT; // shut down clock to SPI1
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g_pASys->ASYNCPRESETCTRLSET = 1UL << 10; // put SPI1 in reset mode
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platform_mcu_powersave_enable();
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return kNoErr;
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}
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extern void DmaAbort(DMA_CHID_T dmaCh);
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volatile uint8_t g_isWlanRx;
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uint32_t g_xferCnt, g_xferDoneCnt;
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OSStatus _prvWlanSPIXfer( bus_transfer_direction_t dir, uint8_t* pTxBuf, uint8_t *pRxBuf, uint16_t buffer_length )
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{
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OSStatus result;
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LPC_SPI_T *pSPI = g_pSPI1;
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uint32_t retry;
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DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) g_pDMA->SRAMBASE;
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platform_mcu_powersave_disable();
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pSPI->STAT = SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD;
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if (buffer_length < 256 || (buffer_length < 512 && dir == BUS_WRITE))
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{
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platform_gpio_output_low( &wifi_spi_pins[WIFI_PIN_SPI_CS] ); /* CS high (to deselect) */
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NVIC_DisableIRQ(SPI1_IRQn);
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if (dir == BUS_READ)
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{
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pSPI->TXCTRL &= ~(1UL<<22);
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while (buffer_length--)
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{
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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pSPI->TXDAT = *pTxBuf++;
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while (!(pSPI->STAT & SPI_STAT_RXRDY));
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*pRxBuf++ = (uint8_t) pSPI->RXDAT;
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}
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}
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else
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{
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pSPI->TXCTRL |= (1UL<<22);
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while (buffer_length--)
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{
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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pSPI->TXDAT = *pTxBuf++;
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}
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}
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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platform_gpio_output_high( &wifi_spi_pins[WIFI_PIN_SPI_CS] ); /* CS high (to deselect) */
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platform_mcu_powersave_enable();
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return 0;
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}
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// Rocky: we use GPIO to control the SSEL level
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if ( dir == BUS_WRITE)
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{
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pSPI->TXCTRL |= 1UL<<22; // ignore RX
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} else {
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pSPI->TXCTRL &= ~(1UL<<22);
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}
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bDMASPITXDoneFlag = false;
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bDMASPIRXDoneFlag = false;
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// init dual-buffer DMA control block
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s_dbDMA.c1Rem = buffer_length;
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s_dbDMA.isToRx = dir == BUS_READ ? 1 : 0;
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s_dbDMA.pC1TxBuf = pTxBuf , s_dbDMA.pC1RxBuf = pRxBuf;
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s_dbDMA.pRxDescs[0] = (DMA_CHDESC_T *) g_pDMA->SRAMBASE + DMACHN_WLAN_RX;
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s_dbDMA.pTxDescs[0] = (DMA_CHDESC_T *) g_pDMA->SRAMBASE + DMACHN_WLAN_TX;
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s_dbDMA.pRxDescs[0]->source = DMA_ADDR(&pSPI->RXDAT);
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s_dbDMA.pTxDescs[0]->dest = DMA_ADDR(&pSPI->TXDAT);
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s_dbDMA.tglBit = 0;
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_prvDbDescCfgNext();
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// wait until DMA channel is not active
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for (retry = 5432; retry !=0; retry--)
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{
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if (0 == (g_pDMA->DMACOMMON[0].ACTIVE & (1UL<<DMACHN_WLAN_RX | 1UL<<DMACHN_WLAN_TX)))
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break;
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}
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if (0 == retry)
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{
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return -1L;
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}
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platform_gpio_output_low( &wifi_spi_pins[WIFI_PIN_SPI_CS] ); /* CS high (to deselect) */
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{
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g_isWlanRx = dir == BUS_READ ? 1 : 0;
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// update channel config and start DMA xfer
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g_xferCnt++;
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// rocky: only start DMA RX if it is for bus read
|
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if (dir == BUS_READ)
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g_pDMA->DMACH[DMACHN_WLAN_RX].XFERCFG = pDesc[DMACHN_WLAN_RX].xfercfg;
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// rocky: DMA TX is ALWAYS initiated
|
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g_pDMA->DMACH[DMACHN_WLAN_TX].XFERCFG = pDesc[DMACHN_WLAN_TX].xfercfg;
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#ifdef USE_WLAN_SPI_SEM
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result = mico_rtos_get_semaphore( &spi_transfer_finished_semaphore, 1000 );
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if (result != kNoErr)
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{
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NVIC_DisableIRQ(DMA_IRQn);
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DmaAbort(DMACHN_WLAN_RX);
|
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DmaAbort(DMACHN_WLAN_TX);
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g_pDMA->DMACOMMON[0].INTA = 1UL<< DMACHN_WLAN_RX | 1UL<<DMACHN_WLAN_TX;
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NVIC_EnableIRQ(DMA_IRQn);
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}
|
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#else
|
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{
|
||||
while(bDMASPITXDoneFlag == false) {
|
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//__WFI();
|
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asm("wfi");
|
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}
|
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while(bDMASPIRXDoneFlag == false) {
|
||||
//__WFI();
|
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asm("wfi");
|
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}
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result = 0;
|
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}
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#endif
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s_dbDMA.tglBit = 0;
|
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g_xferDoneCnt++;
|
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/* Clear the CS pin and the DMA status flag */
|
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}
|
||||
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platform_gpio_output_high( &wifi_spi_pins[WIFI_PIN_SPI_CS] ); /* CS high (to deselect) */
|
||||
|
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platform_mcu_powersave_enable();
|
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|
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return result;
|
||||
}
|
||||
|
||||
OSStatus host_platform_spi_transfer( bus_transfer_direction_t dir, uint8_t* buffer, uint16_t buffer_length )
|
||||
{
|
||||
OSStatus ret = kNoErr;
|
||||
volatile uint32_t retry;
|
||||
for (retry=0; retry < 3; )
|
||||
{
|
||||
|
||||
ret = _prvWlanSPIXfer(dir, buffer, buffer, buffer_length);
|
||||
if (ret != kNoErr)
|
||||
retry++;
|
||||
else
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if 0
|
||||
uint32_t s_buf[3072 / 4];
|
||||
void SpiLongXferTest(void)
|
||||
{
|
||||
uint32_t i;
|
||||
uint16_t *pC2Buf = (uint16_t*) s_buf;
|
||||
LPC_SPI_T *pSPI = LPC_SPI1;
|
||||
pSPI->CFG |= 1UL<<7;
|
||||
|
||||
for (i=0; i<3072/2; i++)
|
||||
pC2Buf[i] = i;
|
||||
|
||||
_prvWlanSPIXfer(BUS_READ, (uint8_t*) 0, (uint8_t*)pC2Buf, 3072);
|
||||
|
||||
pSPI->CFG &= ~(1UL<<7);
|
||||
}
|
||||
#else
|
||||
void SpiLongXferTest(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file wlan_platform.c
|
||||
* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
* @brief This file provide functions called by MICO to wlan RF module
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "platform_config.h"
|
||||
#include "platform_peripheral.h"
|
||||
#include "platform_logging.h"
|
||||
|
||||
/* Used to give a 32k clock to EMW1062 wifi rf module */
|
||||
OSStatus host_platform_init_wlan_powersave_clock( void )
|
||||
{
|
||||
#if 0
|
||||
#if defined ( MICO_USE_WIFI_32K_CLOCK_MCO ) && defined ( MICO_USE_WIFI_32K_PIN )
|
||||
// Magicoe TODO fixed platform_gpio_set_alternate_function( wifi_control_pins[WIFI_PIN_32K_CLK].port, wifi_control_pins[WIFI_PIN_32K_CLK].pin_number, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_MCO );
|
||||
/*
|
||||
Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_32K_OSC);
|
||||
Chip_Clock_EnableRTCOsc();
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 21, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN));
|
||||
Chip_Clock_SetCLKOUTSource(SYSCON_CLKOUTSRC_RTC, 1);
|
||||
*/
|
||||
/* enable LSE output on MCO1 */
|
||||
// Magicoe TODO fixed RCC_MCO1Config( RCC_MCO1Source_LSE, RCC_MCO1Div_1 );
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 21, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN));
|
||||
return kNoErr;
|
||||
#elif defined ( MICO_USE_WIFI_32K_PIN )
|
||||
return host_platform_deinit_wlan_powersave_clock( );
|
||||
#else
|
||||
return kNoErr;
|
||||
#endif
|
||||
#else
|
||||
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 21, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN));
|
||||
return kNoErr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user