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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
This commit is contained in:
OOP
451
mico-os/platform/MCU/LPC5410x/peripherals/platform_spi.c
Normal file
451
mico-os/platform/MCU/LPC5410x/peripherals/platform_spi.c
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@@ -0,0 +1,451 @@
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/**
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******************************************************************************
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* @file MicoDriverSpi.c
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provide SPI driver functions.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "mico_platform.h"
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#include "mico_rtos.h"
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#include "platform.h"
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#include "platform_config.h"
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#include "platform_peripheral.h"
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#include "debug.h"
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/******************************************************
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* Constants
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******************************************************/
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#define MAX_NUM_SPI_PRESCALERS (8)
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/******************************************************
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* Enumerations
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******************************************************/
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/******************************************************
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* Type Definitions
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******************************************************/
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/******************************************************
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* Structures
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******************************************************/
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/******************************************************
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* Static Function Declarations
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******************************************************/
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/******************************************************
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* Variables Definitions
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******************************************************/
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/******************************************************
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* Function Definitions
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******************************************************/
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uint8_t platform_spi_get_port_number( platform_spi_port_t* spi )
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{
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if ( spi == LPC_SPI0 ) {
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return 0;
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}
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else if ( spi == LPC_SPI1 ) {
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return 1;
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}
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// else if ( spi == LPC_SPI2 ) {
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// return 2;
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// }
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else if ( spi == NULL ) {
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return 3;
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}
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else {
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return 0xFF;
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}
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}
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//
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#define SPI_FLASH_CS_LOW Chip_GPIO_SetPinState(LPC_GPIO, 0, 14, 0)
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#define SPI_FLASH_CS_HIGH Chip_GPIO_SetPinState(LPC_GPIO, 0, 14, 1)
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//
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#define SPI_FLASH_MISO_LOW
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#define SPI_FLASH_MISO_HIGH
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#define SPI_FLASH_MISO_GET Chip_GPIO_GetPinState(LPC_GPIO, 0, 13)
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#define SPI_FLASH_MOSI_LOW Chip_GPIO_SetPinState(LPC_GPIO, 0, 12, 0)
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#define SPI_FLASH_MOSI_HIGH Chip_GPIO_SetPinState(LPC_GPIO, 0, 12, 1)
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#define SPI_FLASH_SCK_LOW Chip_GPIO_SetPinState(LPC_GPIO, 0, 11, 0)
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#define SPI_FLASH_SCK_HIGH Chip_GPIO_SetPinState(LPC_GPIO, 0, 11, 1)
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// Magicoe OSStatus platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
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OSStatus platform_spi_init( platform_spi_driver_t* driver, const platform_spi_t* peripheral, const platform_spi_config_t* config )
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{
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// SPI_InitTypeDef spi_init;
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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uint32_t t1; //general var
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require_action_quiet( ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
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require_action_quiet( ( peripheral->port == LPC_SPI0 ), exit, err = kParamErr);
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driver->isRxDone = driver->isTxDone = 0;
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#ifndef NO_MICO_RTOS
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if (driver->sem_xfer_done == 0)
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mico_rtos_init_semaphore(&driver->sem_xfer_done, 1);
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#endif
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// >>> Init Pin mux
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t1 = IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
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if (peripheral->port == LPC_SPI0)
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{
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if (config->speed >= 24000000)
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t1 |= 1UL<<9; // enable fast slew
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g_pIO->PIO[0][11] = IOCON_FUNC1 | t1;/* SPI0_SCK */
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g_pIO->PIO[0][12] = IOCON_FUNC1 | t1; /* SPI0_MOSI */
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g_pIO->PIO[0][13] = IOCON_FUNC1 | t1; /* SPI0_MISO */
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// config CS pin as GPIO
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g_pIO->PIO[config->chip_select->port][config->chip_select->pin_number] = IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
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platform_gpio_output_high(config->chip_select);
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platform_gpio_init(config->chip_select, OUTPUT_PUSH_PULL);
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}
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// <<<
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// >>>
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// initialize SPI peripheral
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{
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uint32_t bv;
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LPC_SPI_T *pSPI = peripheral->port;
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// >>>
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bv = pSPI == LPC_SPI0 ? 1UL << 9 : 1UL<<10;
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g_pASys->ASYNCAPBCLKCTRLSET = bv; // enable clock to SPI
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g_pASys->ASYNCPRESETCTRLSET = bv;
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g_pASys->ASYNCPRESETCTRLCLR = bv;
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// <<<
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// predly | postDly| fraDly | xferDly
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pSPI->DLY = 1UL<<0 | 1UL<<4 | 1UL<<8 | 1UL<<12;
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pSPI->DLY = 0;
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t1 = Chip_Clock_GetAsyncSyscon_ClockRate();
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t1 = (t1 + config->speed - 1) / config->speed;
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pSPI->DIV = t1 - 1; // proper division
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pSPI->TXCTRL = (config->bits - 1) << 24; // 8 bits per frame
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// Enable | master | no loopback
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t1 = 1UL<<0 | 1UL<<2 | 0UL<<7;
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// determine SPI mode
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if (config->mode & SPI_CLOCK_IDLE_HIGH) {
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t1 |= 1UL<<5; // CPOL = 1
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if (t1 & SPI_CLOCK_RISING_EDGE)
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t1 |= 1UL<<4; // CPHA = 1
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} else {
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if (!(t1 & SPI_CLOCK_RISING_EDGE))
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t1 |= 1UL<<4;
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}
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pSPI->CFG = t1;
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}
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// <<<
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g_pDMA->DMACOMMON[0].ENABLESET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
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g_pDMA->DMACOMMON[0].INTENSET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
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g_pDMA->DMACH[peripheral->dmaRxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);
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g_pDMA->DMACH[peripheral->dmaTxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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// Magicoe OSStatus platform_spi_deinit( const platform_spi_t* spi )
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OSStatus platform_spi_deinit( platform_spi_driver_t* driver )
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{
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uint32_t bv;
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OSStatus err = kNoErr;
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platform_spi_t const *peripheral;;
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LPC_SPI_T *pSPI;
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require_action_quiet( ( driver != NULL ) && ( driver->peripheral != NULL ), exit, err = kParamErr);
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peripheral = driver->peripheral , pSPI = peripheral->port;
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bv = pSPI == LPC_SPI0 ? 1UL << 9 : 1UL<<10;
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g_pASys->ASYNCAPBCLKCTRLCLR = bv; // disable clock to SPI
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g_pASys->ASYNCPRESETCTRLSET = bv; // put SPI into reset state
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// disable DMA channels for SPI
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g_pDMA->DMACOMMON[0].ENABLECLR = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
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g_pDMA->DMACOMMON[0].INTENCLR = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
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#ifndef NO_MICO_RTOS
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if (driver->sem_xfer_done != 0)
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mico_rtos_deinit_semaphore(&driver->sem_xfer_done);
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driver->sem_xfer_done = 0;
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#endif
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exit:
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return err;
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}
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/*static*/ platform_spi_driver_t *s_pSPIDrvs[1];
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void OnSPIDmaXferDone(uint32_t spiNdx, uint32_t isRx, uint32_t isErr)
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{
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platform_spi_driver_t *pDrv = s_pSPIDrvs[spiNdx];
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if (isRx) {
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pDrv->isRxDone = 1;
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if (isErr)
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pDrv->xferErr |= 1UL<<1;
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} else {
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pDrv->isTxDone = 1;
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if (isErr)
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pDrv->xferErr |= 1UL<<0;
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}
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#ifndef NO_MICO_RTOS
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if (pDrv->isTxDone) {
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if (!pDrv->isRx || pDrv->isRxDone)
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mico_rtos_set_semaphore(&pDrv->sem_xfer_done);
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}
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#endif
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}
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// Magicoe OSStatus platform_spi_transfer( const platform_spi_t* spi, const platform_spi_config_t* config, const platform_spi_message_segment_t* segments, uint16_t number_of_segments )
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OSStatus platform_spi_transfer( platform_spi_driver_t* driver, const platform_spi_config_t* config, const platform_spi_message_segment_t* segments, uint16_t number_of_segments )
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{
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OSStatus err = kNoErr;
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uint32_t count = 0;
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uint32_t i;
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const platform_spi_message_segment_t *pSeg;
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uint32_t dmaXferLen;
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DMA_CHDESC_T *pTxDesc, *pRxDesc;
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LPC_SPI_T *pSPI;
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uint32_t dmaRxChnNdx, dmaTxChnNdx;
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const uint8_t *pcTx;
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uint8_t *pRx;
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require_action_quiet( ( driver != NULL ) && ( config != NULL ) && ( segments != NULL ) && ( number_of_segments != 0 ), exit, err = kParamErr);
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// save the driver pointer so that in DMA IRQ callback we can access its members
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platform_mcu_powersave_disable();
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pSeg = segments;
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pTxDesc = (DMA_CHDESC_T *) g_pDMA->SRAMBASE + driver->peripheral->dmaTxChnNdx;
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pRxDesc = (DMA_CHDESC_T *) g_pDMA->SRAMBASE + driver->peripheral->dmaRxChnNdx;
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pSPI = driver->peripheral->port;
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if (pSPI == LPC_SPI0)
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s_pSPIDrvs[0] = driver;
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dmaRxChnNdx = driver->peripheral->dmaRxChnNdx , dmaTxChnNdx = driver->peripheral->dmaTxChnNdx;
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driver->xferErr = 0;
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/* Activate chip select */
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platform_gpio_output_low( config->chip_select );
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for ( i = 0; i < number_of_segments; i++, pSeg++ )
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{
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// transfer one seg
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count = pSeg->length;
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if (0 == count)
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continue;
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pcTx = pSeg->tx_buffer , pRx = pSeg->rx_buffer;
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do
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{
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dmaXferLen = count > DMA_MAX_XFER_CNT ? DMA_MAX_XFER_CNT : count;
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count -= dmaXferLen;
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driver->isRxDone = driver->isTxDone = 0;
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#if 0
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{
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if (pRx != 0)
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{
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pSPI->TXCTRL &= ~(1UL<<22);
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if (pSPI->STAT & SPI_STAT_RXRDY)
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pSPI->RXDAT;
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while (dmaXferLen--)
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{
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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pSPI->TXDAT = *pcTx++;
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while (!(pSPI->STAT & SPI_STAT_RXRDY));
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*pRx++ = (uint8_t) pSPI->RXDAT;
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}
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}
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else
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{
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pSPI->TXCTRL |= (1UL<<22);
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while (dmaXferLen--)
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{
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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pSPI->TXDAT = *pcTx++;
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}
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}
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while (!(pSPI->STAT & SPI_STAT_TXRDY));
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}
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#else
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pTxDesc->next = 0;
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pTxDesc->dest = DMA_ADDR(&pSPI->TXDAT);
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pTxDesc->source = DMA_ADDR(pcTx) + dmaXferLen - 1;
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pTxDesc->xfercfg = DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA |
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DMA_XFERCFG_SWTRIG | DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 |
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DMA_XFERCFG_DSTINC_0 | DMA_XFERCFG_XFERCOUNT(dmaXferLen);
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if (pRx != 0)
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{
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pSPI->TXCTRL &= ~(1UL<<22);
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driver->isRx = 1;
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pRxDesc->next = 0;
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pRxDesc->source = DMA_ADDR(&pSPI->RXDAT);
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pRxDesc->dest = DMA_ADDR(pRx) + dmaXferLen - 1;
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pRxDesc->xfercfg = DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA |
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DMA_XFERCFG_SWTRIG | DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_DSTINC_1 |
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DMA_XFERCFG_SRCINC_0 | DMA_XFERCFG_XFERCOUNT(dmaXferLen);
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// start RX DMA
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g_pDMA->DMACH[dmaRxChnNdx].XFERCFG = pRxDesc->xfercfg;
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} else {
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driver->isRx = 0;
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pSPI->TXCTRL |= (1UL<<22);
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}
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// start TX DMA
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g_pDMA->DMACH[dmaTxChnNdx].XFERCFG = pTxDesc->xfercfg;
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#ifndef NO_MICO_RTOS
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mico_rtos_get_semaphore(&driver->sem_xfer_done, MICO_WAIT_FOREVER);
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#else
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while(1)
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{
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if (driver->isTxDone)
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{
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if (!driver->isRx || driver->isRxDone)
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break;
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}
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// __WFI();
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mico_rtos_delay_milliseconds(1);
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}
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#endif
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#endif
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if (driver->xferErr)
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{
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err = kGeneralErr;
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break;
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}
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// >>> update read and/or write pointers
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pcTx += dmaXferLen;
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if (pRx != 0)
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pRx += dmaXferLen;
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// <<<
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} while (count);
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}
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platform_gpio_output_high( config->chip_select );
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exit:
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platform_mcu_powersave_enable( );
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return err;
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}
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uint8_t SPI_SendData(uint8_t data)
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{
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uint32_t i = 0, j = 0;
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uint8_t ret = 0;
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for(i=0; i<8; i++) {
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ret = ((ret<<1)&0xFE);
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SPI_FLASH_SCK_LOW;
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for(j=0; j<10; j++);
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if(data&0x80) {
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SPI_FLASH_MOSI_HIGH;
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}
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else{
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SPI_FLASH_MOSI_LOW;
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}
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for(j=0; j<10; j++);
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SPI_FLASH_SCK_HIGH;
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for(j=0; j<10; j++);
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data = (data<<1);
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if((SPI_FLASH_MISO_GET&0x01) == 1) {
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ret = ret|0x01;
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}
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else {
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ret &= 0xFE;
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}
|
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}
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return ret;
|
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}
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//
|
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//static uint16_t spi_transfer( const platform_spi_t* spi, uint16_t data )
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//{
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||||
// uint16_t ret = 0;
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// ret = SPI_SendData(data);
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//// printf("SPI RW %x %x\r\n", tmp, ret);
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// return ret;
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//}
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platform_spi_message_segment_t s_segs[3];
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#if 0
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#pragma data_alignment=16
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uint8_t s_spiTestbuf[3200];
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|
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extern const mico_spi_device_t mico_spi_flash;
|
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extern platform_spi_driver_t platform_spi_drivers[];
|
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extern const platform_gpio_t platform_gpio_pins[];
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||||
|
||||
void SPIDrvTest(void)
|
||||
{
|
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platform_spi_config_t cfg;
|
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s_segs[0].length = 1024;
|
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s_segs[0].tx_buffer = (const void*) 0;
|
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s_segs[0].rx_buffer = s_spiTestbuf;
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s_segs[1].length = 1025;
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s_segs[1].tx_buffer = (const void*) 0x1000;
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s_segs[1].rx_buffer = s_spiTestbuf;
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s_segs[2].length = sizeof(s_spiTestbuf);
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s_segs[2].tx_buffer = (const void*) 0x4000;
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s_segs[2].rx_buffer = s_spiTestbuf;
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||||
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cfg.speed = mico_spi_flash.speed;
|
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cfg.chip_select = platform_gpio_pins + mico_spi_flash.chip_select;
|
||||
cfg.mode = mico_spi_flash.mode;
|
||||
cfg.bits = mico_spi_flash.bits;
|
||||
|
||||
// >>>
|
||||
{
|
||||
|
||||
platform_spi_driver_t *pDrv = &platform_spi_drivers[MICO_SPI_0];
|
||||
platform_spi_t const *pHw = pDrv->peripheral;
|
||||
platform_spi_init(pDrv, pHw, &cfg);
|
||||
platform_spi_deinit(pDrv);
|
||||
platform_spi_init(pDrv, pHw, &cfg);
|
||||
g_pSPI0->CFG |= 1UL << 7;
|
||||
platform_spi_transfer(pDrv, &cfg, s_segs + 0, 3);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void SPIDrvTest(void) {}
|
||||
#endif
|
||||
|
||||
// end file --- MG.Niu ---
|
||||
Reference in New Issue
Block a user