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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
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OOP
171
mico-os/platform/MCU/LPC5410x/peripherals/Libraries/dma_5410x.c
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171
mico-os/platform/MCU/LPC5410x/peripherals/Libraries/dma_5410x.c
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/*
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* @brief DMA driver declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2015
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
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function if a DMA SRAM table is needed. This table is correctly aligned for
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the DMA controller. */
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#if defined(__CC_ARM)
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/* Keil alignement to 512 bytes */
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__align(512) DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
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#endif /* defined (__CC_ARM) */
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/* IAR support */
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#if defined(__ICCARM__)
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/* IAR EWARM alignement to 512 bytes */
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#pragma data_alignment=512
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DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
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#endif /* defined (__ICCARM__) */
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#if defined( __GNUC__ )
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/* GNU alignement to 512 bytes */
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DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL] __attribute__ ((aligned(512)));
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#endif /* defined (__GNUC__) */
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Set DMA transfer register interrupt bits (safe) */
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void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
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{
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uint32_t temp;
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/* Read and write values may not be the same, write 0 to
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undefined bits */
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temp = pDMA->DMACH[ch].XFERCFG & ~0xFC000CC0;
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pDMA->DMACH[ch].XFERCFG = temp | mask;
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}
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/* Clear DMA transfer register interrupt bits (safe) */
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void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask)
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{
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uint32_t temp;
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/* Read and write values may not be the same, write 0 to
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undefined bits */
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temp = pDMA->DMACH[ch].XFERCFG & ~0xFC000CC0;
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pDMA->DMACH[ch].XFERCFG = temp & ~mask;
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}
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/* Update the transfer size in an existing DMA channel transfer configuration */
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void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans)
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{
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Chip_DMA_ClearTranBits(pDMA, ch, (0x3FF << 16));
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Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_XFERCOUNT(trans));
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}
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/* Sets up a DMA channel with the passed DMA transfer descriptor */
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bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc)
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{
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bool good = false;
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DMA_CHDESC_T *pDesc = (DMA_CHDESC_T *) pDMA->SRAMBASE;
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if ((Chip_DMA_GetActiveChannels(pDMA) & (1 << ch)) == 0) {
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/* Channel is not active, so update the descriptor */
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pDesc[ch] = *desc;
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good = true;
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}
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return good;
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}
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/**
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* Initialize DMA parameters specific to a channel
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*
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* @param channel
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* @param src_address
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* @param dst_address
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* @param xfr_width
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* @param length_bytes
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*/
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void Chip_DMA_InitChannel( DMA_CHID_T channel, uint32_t src_address, uint32_t src_increment,
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uint32_t dst_address, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes, uint32_t priority)
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{
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Chip_DMA_EnableChannel(LPC_DMA, channel);
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Chip_DMA_EnableIntChannel(LPC_DMA, channel);
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Chip_DMA_SetupChannelConfig(LPC_DMA, channel, DMA_CFG_PERIPHREQEN |
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DMA_CFG_CHPRIORITY(priority));
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if (src_increment != DMA_XFERCFG_SRCINC_0) {
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Chip_DMA_Table[channel].source = DMA_ADDR((src_address + length_bytes)
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- (1UL << xfr_width));
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} else {
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Chip_DMA_Table[channel].source = DMA_ADDR(src_address);
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}
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if (dst_increment != DMA_XFERCFG_DSTINC_0) {
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Chip_DMA_Table[channel].dest = DMA_ADDR((dst_address + length_bytes)
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- (1UL << xfr_width));
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} else {
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Chip_DMA_Table[channel].dest = DMA_ADDR(dst_address);
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}
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Chip_DMA_Table[channel].next = DMA_ADDR(0);
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}
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/**
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* Start the DMA transfer
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*
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* @param channel
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* @param src_increment
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* @param dst_increment
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* @param xfr_width
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* @param length_bytes
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*/
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void Chip_DMA_StartTransfer(DMA_CHID_T channel, uint32_t src_increment, uint32_t dst_increment, uint32_t xfr_width, uint32_t length_bytes)
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{
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uint32_t xfer_count;
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/* Calculate transfer_count ( length in terms of transfers) */
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xfer_count = (xfr_width == DMA_XFERCFG_WIDTH_8) ? length_bytes :
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(xfr_width == DMA_XFERCFG_WIDTH_16) ? (length_bytes >> 1) :
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(length_bytes >> 2);
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Chip_DMA_SetupChannelTransfer(LPC_DMA, channel,
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(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SETINTA | DMA_XFERCFG_SWTRIG |
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xfr_width | src_increment | dst_increment |
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DMA_XFERCFG_XFERCOUNT(xfer_count)));
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}
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