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https://github.com/oopuuu/zTC1.git
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修改了Web后台的部分界面，增加了HAmqtt中的总电量传感器，后台新增mqtt上报频率设置
This commit is contained in:
OOP
378
mico-os/platform/MCU/LPC5410x/EWARM/startup_lpc54100_EWARM.s
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378
mico-os/platform/MCU/LPC5410x/EWARM/startup_lpc54100_EWARM.s
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@@ -0,0 +1,378 @@
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;/*****************************************************************************
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; * @file: startup_LPC5410x.s
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; * @purpose: CMSIS Cortex-M4/M0+ Core Device Startup File
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; * for the NXP LPC5410x Device Series (manually edited)
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; * @version: V1.00
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; * @date: 19. October 2009
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; *
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; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN vPortSVCHandler
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EXTERN xPortPendSVHandler
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EXTERN hard_fault_handler_c
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EXTERN xPortSysTickHandler
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD MemManage_Handler
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DCD BusFault_Handler
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DCD UsageFault_Handler
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__vector_table_0x1c
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DCD 0 ; Checksum of the first 7 words
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DCD 0
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DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot
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DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot
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DCD SVC_Handler
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DCD DebugMon_Handler
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD WDT_IRQHandler ; Watchdog
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD Reserved_IRQHandler ; Reserved
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DCD DMA_IRQHandler ; DMA Controller
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DCD GINT0_IRQHandler ; GPIO Group0 Interrupt
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DCD PIN_INT0_IRQHandler ; PIO INT0
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DCD PIN_INT1_IRQHandler ; PIO INT1
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DCD PIN_INT2_IRQHandler ; PIO INT2
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DCD PIN_INT3_IRQHandler ; PIO INT3
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DCD UTICK_IRQHandler ; UTICK timer
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DCD MRT_IRQHandler ; Multi-Rate Timer
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DCD CT32B0_IRQHandler ; CT32B0
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DCD CT32B1_IRQHandler ; CT32B1
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DCD CT32B2_IRQHandler ; CT32B2
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DCD CT32B3_IRQHandler ; CT32B3
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DCD CT32B4_IRQHandler ; CT32B4
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DCD SCT0_IRQHandler ; Smart Counter Timer
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DCD UART0_IRQHandler ; UART0
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DCD UART1_IRQHandler ; UART1
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DCD UART2_IRQHandler ; UART2
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DCD UART3_IRQHandler ; UART3
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DCD I2C0_IRQHandler ; I2C0 controller
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DCD I2C1_IRQHandler ; I2C1 controller
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DCD I2C2_IRQHandler ; I2C2 controller
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DCD SPI0_IRQHandler ; SPI0 controller
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DCD SPI1_IRQHandler ; SPI1 controller
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DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt
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DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt
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DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed
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DCD RTC_IRQHandler ; RTC Timer
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DCD Reserved_IRQHandler ; Reserved
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DCD MAILBOX_IRQHandler ; Mailbox
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DCD GINT1_IRQHandler ; GPIO Group1 Interrupt
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DCD PIN_INT4_IRQHandler ; PIO INT4
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DCD PIN_INT5_IRQHandler ; PIO INT5
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DCD PIN_INT6_IRQHandler ; PIO INT6
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DCD PIN_INT7_IRQHandler ; PIO INT7
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD Reserved_IRQHandler ; Reserved
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DCD RIT_IRQHandler ; RITimer
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DCD Reserved41_IRQHandler ; Reserved
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DCD Reserved42_IRQHandler ; Reserved
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DCD Reserved43_IRQHandler ; Reserved
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DCD Reserved44_IRQHandler ; Reserved
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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#if !defined(SLAVEBOOT)
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DATA
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cpu_id EQU 0xE000ED00
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cpu_ctrl EQU 0x40000300
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coproc_boot EQU 0x40000304
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coproc_stack EQU 0x40000308
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rel_vals
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DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack
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DC16 0xFFF, 0xC24
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#endif
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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; Reset Handler - shared for both cores
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Reset_Handler
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#if !defined(SLAVEBOOT)
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; Both the M0+ and M4 core come via this shared startup code,
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; but the M0+ and M4 core have different vector tables.
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; Determine if the core executing this code is the master or
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; the slave and handle each core state individually.
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shared_boot_entry
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; >>> Rocky, Preare all SRAM blocks, in case MSP points to unpowered SRAM
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ldr r0, =0x40000218
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ldr r1, =0x1E000
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str r1, [r0] ; SYSCON->PDRUNCFGCLR = 0x1E000
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ldr r0, =0x400000C8
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ldr r1, =0x18
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str r1, [r0] ; SYSCON->AHBCLKCTRLSET[0] = 0x18
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; <<<
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LDR r6, =rel_vals
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MOVS r4, #0 ; Flag for slave core (0)
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MOVS r5, #1
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; Determine which core (M0+ or M4) this code is running on
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; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
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get_current_core_id
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LDR r0, [r6, #0]
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LDR r1, [r0] ; r1 = CPU ID status
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LSRS r1, r1, #4 ; Right justify 12 CPU ID bits
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LDRH r2, [r6, #16] ; Mask for CPU ID bits
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ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID
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LDRH r3, [r6, #18] ; Mask for CPU ID bits
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CMP r3, r2 ; Core ID matches M4 identifier
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BNE get_master_status
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MOV r4, r5 ; Set flag for master core (1)
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; Determine if M4 core is the master or slave
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; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
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get_master_status
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LDR r0, [r6, #4]
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LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status
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ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
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; Select boot based on selected master core and core ID
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select_boot
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EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave)
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BNE slave_boot
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B normal_boot
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; Slave boot
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slave_boot
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LDR r0, [r6, #8]
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LDR r2, [r0] ; r1 = SYSCON co-processor boot address
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CMP r2, #0 ; Slave boot address = 0 (not set up)?
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BEQ cpu_sleep
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LDR r0, [r6, #12]
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LDR r1, [r0] ; r5 = SYSCON co-processor stack address
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MOV sp, r1 ; Update slave CPU stack pointer
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; Be sure to update VTOR for the slave MCU to point to the
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; slave vector table in boot memory
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BX r2 ; Jump to slave boot address
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; Slave isn't yet setup for system boot from the master
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; so sleep until the master sets it up and then reboots it
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cpu_sleep
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MOV sp, r5 ; Will force exception if something happens
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cpu_sleep_wfi
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WFI ; Sleep forever until master reboots
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B cpu_sleep_wfi
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#endif ; defined(SLAVEBOOT)
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; Normal boot for master/slave
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normal_boot
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LDR r0, =SystemInit
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BLX r0
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LDR r0, =__iar_program_start
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BX r0
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; For cores with SystemInit() or __iar_program_start(), the code will sleep the MCU
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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PUBWEAK SystemInit
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SECTION .text:CODE:REORDER(1)
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SystemInit
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BX LR
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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TST LR, #4
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ITE EQ
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MRSEQ R0, MSP
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MRSNE R0, PSP
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B hard_fault_handler_c
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B vPortSVCHandler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B xPortPendSVHandler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B xPortSysTickHandler
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PUBWEAK Reserved_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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Reserved_IRQHandler
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B .
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PUBWEAK WDT_IRQHandler ; Watchdog
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PUBWEAK BOD_IRQHandler ; Brown Out Detect
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PUBWEAK DMA_IRQHandler ; DMA Controller
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PUBWEAK GINT0_IRQHandler ; GPIO Group0 Interrupt
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PUBWEAK PIN_INT0_IRQHandler ; PIO INT0
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PUBWEAK PIN_INT1_IRQHandler ; PIO INT1
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PUBWEAK PIN_INT2_IRQHandler ; PIO INT2
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PUBWEAK PIN_INT3_IRQHandler ; PIO INT3
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PUBWEAK UTICK_IRQHandler ; UTICK timer
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PUBWEAK MRT_IRQHandler ; Multi-Rate Timer
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PUBWEAK CT32B0_IRQHandler ; CT32B0
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PUBWEAK CT32B1_IRQHandler ; CT32B1
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PUBWEAK CT32B2_IRQHandler ; CT32B2
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PUBWEAK CT32B3_IRQHandler ; CT32B3
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PUBWEAK CT32B4_IRQHandler ; CT32B4
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PUBWEAK UART0_IRQHandler ; UART0
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PUBWEAK SCT0_IRQHandler ; Smart Counter Timer
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PUBWEAK UART1_IRQHandler ; UART1
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PUBWEAK UART2_IRQHandler ; UART2
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PUBWEAK UART3_IRQHandler ; UART3
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PUBWEAK I2C0_IRQHandler ; I2C0 controller
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PUBWEAK I2C1_IRQHandler ; I2C1 controller
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PUBWEAK I2C2_IRQHandler ; I2C2 controller
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PUBWEAK SPI0_IRQHandler ; SPI0 controller
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PUBWEAK SPI1_IRQHandler ; SPI1 controller
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PUBWEAK ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt
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PUBWEAK ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt
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PUBWEAK ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed
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PUBWEAK RTC_IRQHandler ; RTC Timer
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PUBWEAK MAILBOX_IRQHandler ; Mailbox
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PUBWEAK GINT1_IRQHandler ; GPIO Group1 Interrupt
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PUBWEAK PIN_INT4_IRQHandler ; PIO INT4
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PUBWEAK PIN_INT5_IRQHandler ; PIO INT5
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PUBWEAK PIN_INT6_IRQHandler ; PIO INT6
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PUBWEAK PIN_INT7_IRQHandler ; PIO INT7
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PUBWEAK RIT_IRQHandler ; RITimer
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PUBWEAK Reserved41_IRQHandler ; Reserved
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PUBWEAK Reserved42_IRQHandler ; Reserved
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PUBWEAK Reserved43_IRQHandler ; Reserved
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PUBWEAK Reserved44_IRQHandler ; Reserved
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WDT_IRQHandler ; Watchdog
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BOD_IRQHandler ; Brown Out Detect
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DMA_IRQHandler ; DMA Controller
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GINT0_IRQHandler ; GPIO Group0 Interrupt
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PIN_INT0_IRQHandler ; PIO INT0
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PIN_INT1_IRQHandler ; PIO INT1
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PIN_INT2_IRQHandler ; PIO INT2
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PIN_INT3_IRQHandler ; PIO INT3
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UTICK_IRQHandler ; UTICK timer
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MRT_IRQHandler ; Multi-Rate Timer
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CT32B0_IRQHandler ; CT32B0
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CT32B1_IRQHandler ; CT32B1
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CT32B2_IRQHandler ; CT32B2
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CT32B3_IRQHandler ; CT32B3
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CT32B4_IRQHandler ; CT32B4
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UART0_IRQHandler ; UART0
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SCT0_IRQHandler ; Smart Counter Timer
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UART1_IRQHandler ; UART1
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UART2_IRQHandler ; UART2
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UART3_IRQHandler ; UART3
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I2C0_IRQHandler ; I2C0 controller
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I2C1_IRQHandler ; I2C1 controller
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I2C2_IRQHandler ; I2C2 controller
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SPI0_IRQHandler ; SPI0 controller
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SPI1_IRQHandler ; SPI1 controller
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ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt
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ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt
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ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed
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RTC_IRQHandler ; RTC Timer
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MAILBOX_IRQHandler ; Mailbox
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GINT1_IRQHandler ; GPIO Group1 Interrupt
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PIN_INT4_IRQHandler ; PIO INT4
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PIN_INT5_IRQHandler ; PIO INT5
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PIN_INT6_IRQHandler ; PIO INT6
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PIN_INT7_IRQHandler ; PIO INT7
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RIT_IRQHandler ; RITimer
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Reserved41_IRQHandler ; Reserved
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Reserved42_IRQHandler ; Reserved
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Reserved43_IRQHandler ; Reserved
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Reserved44_IRQHandler ; Reserved
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Default_Handler:
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B .
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END
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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