修改了Web后台的部分界面,增加了HAmqtt中的总电量传感器,后台新增mqtt上报频率设置

This commit is contained in:
OOP
2025-03-03 21:49:41 +08:00
parent e1e00b60ce
commit 9f9d4c7a56
4468 changed files with 1473046 additions and 10728 deletions

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#
# UNPUBLISHED PROPRIETARY SOURCE CODE
# Copyright (c) 2016 MXCHIP Inc.
#
# The contents of this file may not be disclosed to third parties, copied or
# duplicated in any form, in whole or in part, without the prior written
# permission of MXCHIP Corporation.
#
init
reset halt

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# script for stm32f2x family
#
# stm32 devices support both JTAG and SWD transports.
#
source [find mico-os/makefiles/OpenOCD/interface/swj-dp.tcl]
source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]
set CHIP_FLASH_START 0x08000000
set CHIP_RAM_START 0x20000000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32f2x
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x10000
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
adapter_khz 10000
adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0033
# Section 32.6.3 - corresponds to Cortex-M3 r2p0
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
if { [info exists BSTAPID] } {
set _BSTAPID $BSTAPID
} else {
# See STM Document RM0033
# Section 32.6.2
#
set _BSTAPID 0x06411041
}
if {[using_jtag]} {
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME -rtos auto
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
#Reset target when gdb attaches
$_TARGETNAME configure -event gdb-attach { reset halt; sleep 1; mww 0xE0042004 3; mww 0xE0042008 0xffffffff }
#shutdown OpenOCD daemon when gdb detaches
$_TARGETNAME configure -event gdb-detach { mww 0xE0042008 0x00000000; reset halt; sleep 5; resume; shutdown }
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event examine-end {
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
mww 0xE0042008 0x00001800
}
$_TARGETNAME configure -event trace-config {
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
proc jtag_init {} {
global _TARGETNAME
# assert both resets; equivalent to power-on reset
jtag_reset 1 1
sleep 1
jtag_reset 0 1
# Examine scanchain
jtag arp_init
$_TARGETNAME arp_examine
# Force STM32 to allow debugging whilst sleeping and in stop-mode
mww 0xE0042004 3
# Set flags to cause timer based peripherals to stop during breakpoints.
mww 0xE0042008 0xffffffff
reset halt
poll on
}

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#
# UNPUBLISHED PROPRIETARY SOURCE CODE
# Copyright (c) 2016 MXCHIP Inc.
#
# The contents of this file may not be disclosed to third parties, copied or
# duplicated in any form, in whole or in part, without the prior written
# permission of MXCHIP Corporation.
#
# default ports
telnet_port 4444
gdb_port 3333
gdb_memory_map enable
init