修改了Web后台的部分界面,增加了HAmqtt中的总电量传感器,后台新增mqtt上报频率设置

This commit is contained in:
OOP
2025-03-03 21:49:41 +08:00
parent e1e00b60ce
commit 9f9d4c7a56
4468 changed files with 1473046 additions and 10728 deletions

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000;
define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x10005FFF;
define symbol __ICFEDIT_region_FWLOADER_start__ = 0x10006000;
define symbol __ICFEDIT_region_FWLOADER_end__ = 0x1000DFFF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x1000E000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1006FFFF;
/*-Sizes-*/
/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
/*define symbol __ICFEDIT_size_heap__ = 0x800;*/
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region FWLOADER_region = mem:[from __ICFEDIT_region_FWLOADER_start__ to __ICFEDIT_region_FWLOADER_end__];
define region IMG2_TEMP_region = mem:[from __ICFEDIT_region_IMG2_TEMP_start__ to __ICFEDIT_region_IMG2_TEMP_end__];
/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
/*define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };*/
//initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
//do not initialize { section * };
//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/
//place in TCM_region { readwrite };
/****************************************
* ROM Section config *
****************************************/
keep { section .rom };
place at start of ROM_region { readonly, section .rom };
/****************************************
* BD RAM Section config *
****************************************/
keep { section .ram_dedecated_vector_table* };
define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
keep { section .ram_user_define_irq_table* };
define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
keep { section .ram_user_define_data_table* };
define block .user_data_table with fixed order{section .ram_user_define_data_table*};
define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o,
section .hal.ram.bss* object hal_pinmux.o,
section .hal.ram.bss* object diag.o,
section .hal.ram.bss* object rtl8195a_ssi_rom.o,
section .hal.ram.bss* object rtl8195a_gpio.o,
section .hal.ram.bss*,
section .timer2_7_vector_table.data*,
section .infra.ram.bss*,
section .mon.ram.bss*,
section .wlan_ram_map* object rom_wlan_ram_map.o,
section .wlan_ram_map*,
section .libc.ram.bss*
};
define block IMAGE1 with fixed order { section LOADER };
keep { section .fwloader.start_ram.data* };
define block .fwloader.start.table1 with fixed order{ section .fwloader.start_ram.data* };
keep { section .fwloader.validate.rodata* };
define block .fwloader.start.table2 with fixed order{ section .fwloader.validate.rodata* };
keep { section .fwloader.ram.data* };
define block .fwloader_ram.data with fixed order{ section .fwloader.ram.data*,
section .data*,
// section .bss*,
section .rodata*
};
define block .fwloader_ram.bss with fixed order{
section .bss*
};
keep { section .fwloader.ram.start* };
define block .fwloader_ram.text with fixed order{ section .fwloader.ram.start*,
section .text*
};
define block .spi_flash.data with fixed order{ section .hal.flash.data*, section .hal.ram.data*, section .hal.gpio.data* };
define block .spi_flash.text with fixed order{ section .hal.ram.text*, section .hal.flash.text*, section .hal.gpio.text*, };
define block FWLOADER with fixed order { block .fwloader.start.table1,
block .fwloader.start.table2,
block .fwloader_ram.text,
block .fwloader_ram.data,
block .fwloader_ram.bss,
block .spi_flash.data,
block .spi_flash.text
};
define block .updata_for_ota.data with fixed order{ section .bss* object Update_for_OTA.o };
keep { section .image2.ram.data* };
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
keep { section .image2.validate.rodata*};
define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*};
define block .ram_image2.text with fixed order{ section .infra.ram.start*,
section .mon.ram.text*
};
define block .heap with fixed order{ section .heap* };
place at start of BD_RAM_region { readwrite,
block .vector_table,
block .user_vector_table,
block .user_data_table,
block .rom.bss,
block IMAGE1,
block .heap
};
place at start of FWLOADER_region { readwrite, block FWLOADER };
place at end of IMG2_TEMP_region { readwrite, block .updata_for_ota.data};
define block .ram.data with fixed order{ section .iar.init_table };
define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
define block .ram.bss with fixed order{
section COMMON,
section .bdsram.data*
};
define block .bf_data with fixed order{ section .bfsram.data* };
place at start of IMG2_TEMP_region { readwrite,
block IMAGE2,
block .ram.bss,
block .bf_data
};
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
// unnecessay symbol
define exported symbol ShowRamBuildInfo=0;
define exported symbol En32KCalibration=0;
define exported symbol _AppStart=0;
define exported symbol vPortSVCHandler=0;
define exported symbol xPortSysTickHandler=0;
define exported symbol xPortPendSVHandler=0;
define exported symbol vTaskDelete=0;
define exported symbol RtlUpSemaFromISR=0;

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#define UTS_VERSION "2016/02/25-11:07:14"
#define RTL8195AFW_COMPILE_TIME "2016/02/25-11:07:14"
#define RTL8195AFW_COMPILE_BY "yangsw"
#define RTL8195AFW_COMPILE_HOST "yangshiwei-mico"
#define RTL8195AFW_COMPILE_DOMAIN
#define RTL195AFW_COMPILER "IAR compiler"

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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "build_info.h"
#include "PinNames.h"
#include "serial_api.h"
extern void serial_init (serial_t *obj, PinName tx, PinName rx);
extern void serial_free (serial_t *obj);
extern void serial_baud (serial_t *obj, int baudrate);
extern void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
extern int main(void);
void iar_data_init_fw_loader(void);
void fw_loader_main(void);// __attribute__ ((weak));
#pragma section=".image2.start.table1"
#pragma section=".fwloader_ram.bss"
FW_LOADER_START_RAM_FUN_SECTION
RAM_START_FUNCTION gFWLoaderEntryFun0 = {fw_loader_main};
u8* __image4_entry_func__;
u8* __image4_validate_code__;
u8* __fwloader_bss_start__;
u8* __fwloader_bss_end__;
FW_LOADER_VALID_PATTEN_SECTION const u8 RAM_FW_LOADER_VALID_PATTEN[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
/**
* @brief Main program.
* @param None
* @retval None
*/
void fw_loader_main(void)
{
#if defined ( __ICCARM__ )
iar_data_init_fw_loader();
#endif
u32 Image2Len, Image2Addr, ImageIndex, SpicBitMode, SpicImageIndex;
u32 Image2LoadAddr = 0x13000;
DBG_8195A("===== Enter FW Loader Image ====\n");
#ifdef BOOTLOADER
main();
#endif
IGMAE4:
PRAM_START_FUNCTION Image4EntryFun=(PRAM_START_FUNCTION)__image4_entry_func__;
Image2Len = HAL_READ32(SPI_FLASH_BASE, Image2LoadAddr);
Image2Addr = HAL_READ32(SPI_FLASH_BASE, (Image2LoadAddr+0x4));
DBG_8195A("Flash FW Loader:Addr 0x%x, Len %d, Load to SRAM 0x%x\n", Image2LoadAddr, Image2Len, Image2Addr);
SpicImageIndex = 0;
for (ImageIndex = 0x10 + Image2LoadAddr; ImageIndex < (Image2Len + Image2LoadAddr + 0x10); ImageIndex = ImageIndex + 4) {
HAL_WRITE32(Image2Addr, SpicImageIndex,
HAL_READ32(SPI_FLASH_BASE, ImageIndex));
SpicImageIndex += 4;
}
#ifdef CONFIG_SDR_EN
u32 Image3LoadAddr;
u32 Image3Len;
u32 Image3Addr;
Image3LoadAddr = Image2LoadAddr + Image2Len+0x10;
Image3Len = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr);
Image3Addr = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr + 0x4);
if( (Image3Len==0xFFFFFFFF) || (Image3Len==0) || (Image3Addr!=0x30000000)){
DBG_8195A("No Image3\n\r");
}else{
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",Image3Len, Image3Addr);
SpicImageIndex = 0;
for (ImageIndex = 0x10 + Image3LoadAddr;
ImageIndex < (Image3Len + Image3LoadAddr + 0x10);
ImageIndex = ImageIndex + 4) {
HAL_WRITE32(Image3Addr, SpicImageIndex,
HAL_READ32(SPI_FLASH_BASE, ImageIndex));
SpicImageIndex += 4;
}
}
#endif
//3 3) Jump to image 4
DBG_8195A("InfraStart: %p, Img2 Sign %s \n", __image4_entry_func__, (char*)__image4_validate_code__);
if (_strcmp((char *)__image4_validate_code__, "RTKWin")) {
while (1) {
DBG_8195A("Invalid Image4 Signature\n");
RtlConsolRom(1000);//each delay is 100us
}
}
#ifdef BOOTLOADER
deinit_platform_bootloader();
#endif
Image4EntryFun->RamStartFun();
}
void iar_data_init_fw_loader(void)
{
__image4_entry_func__ = (u8*)__section_begin(".image2.start.table1");
__image4_validate_code__ = __image4_entry_func__+4;//(u8*)__section_begin(".image2.start.table2");
__fwloader_bss_start__ = (u8*)__section_begin(".fwloader_ram.bss");
__fwloader_bss_end__ = (u8*)__section_end(".fwloader_ram.bss");
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000;
define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
define symbol __ICFEDIT_region_FWLOADER_start__ = 0x10006000;
define symbol __ICFEDIT_region_FWLOADER_end__ = 0x1000DFFF;
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x1000E000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000;
define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF;
/*-Sizes-*/
/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
/*define symbol __ICFEDIT_size_heap__ = 0x800;*/
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
define region FWLOADER_region = mem:[from __ICFEDIT_region_FWLOADER_start__ to __ICFEDIT_region_FWLOADER_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
/*define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };*/
//initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
//do not initialize { section * };
//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/
place in TCM_region { readwrite };
/****************************************
* ROM Section config *
****************************************/
keep { section .rom };
place at start of ROM_region { readonly, section .rom };
/****************************************
* BD RAM Section config *
****************************************/
keep { section .ram_dedecated_vector_table* };
define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
keep { section .ram_user_define_irq_table* };
define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
keep { section .ram_user_define_data_table* };
define block .user_data_table with fixed order{section .ram_user_define_data_table*};
define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o,
section .hal.ram.bss* object hal_pinmux.o,
section .hal.ram.bss* object diag.o,
section .hal.ram.bss* object rtl8195a_ssi_rom.o,
section .hal.ram.bss* object rtl8195a_gpio.o,
section .hal.ram.bss*,
section .timer2_7_vector_table.data*,
section .infra.ram.bss*,
section .mon.ram.bss*,
section .wlan_ram_map* object rom_wlan_ram_map.o,
section .wlan_ram_map*,
section .libc.ram.bss*,
};
keep { section .start.ram.data* };
define block .ram.start.table with fixed order{ section .start.ram.data* };
keep { section .image1.validate.rodata* };
keep { section .infra.ram.data* };
keep { section .timer.ram.data* };
keep { section .hal.ram.data* };
define block .ram_image1.data with fixed order{ section .image1.validate.rodata*,
section .infra.ram.data*,
section .timer.ram.data*,
section .cutb.ram.data*,
section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
section .cutc.ram.data*,
section .hal.ram.data*
};
define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
section .hal.sdrc.data*
};
define block .ram_image1.text with fixed order{ section .hal.ram.text*,
section .hal.sdrc.text*,
//section .text* object startup.o,
section .infra.ram.text*,
};
define block IMAGE1 with fixed order { section LOADER };
define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
place at start of ROM_USED_RAM_region { readwrite,
block .vector_table,
block .user_vector_table,
block .user_data_table,
block .rom.bss,
block IMAGE1
};
keep { section .fwloader.start_ram.data* };
define block .fwloader.start.table1 with fixed order{ section .fwloader.start_ram.data* };
keep { section .fwloader.validate.rodata* };
define block .fwloader.start.table2 with fixed order{ section .fwloader.validate.rodata* };
//keep { section .fwloader.ram.data* };
//define block .fwloader_ram.data with fixed order{ section .fwloader.ram.data*,
// section .data* object fw_loader_main.o,
// section .bss* object fw_loader_main.o,
// section .rodata* object fw_loader_main.o
// };
//keep { section .fwloader.ram.start* };
//define block .fwloader_ram.text with fixed order{
// section .text* object fw_loader_main.o
// };
define block FWLOADER with fixed order { block .fwloader.start.table1,
block .fwloader.start.table2,
// block .fwloader_ram.text,
// block .fwloader_ram.data
};
place at start of FWLOADER_region { readwrite, block FWLOADER };
keep { section .image2.ram.data* };
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
keep { section .image2.validate.rodata*, section .custom.validate.rodata* };
define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* };
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY };
define block .ram_image2.text with fixed order{ section .infra.ram.start*,
section .rodata*,
block CPP_INIT,
section .mon.ram.text*,
section .hal.flash.text*,
section .hal.gpio.text*,
section .text*,
section CODE,
section .otg.rom.text,
section Veneer object startup.o,
section __DLIB_PERTHREAD,
//section .mdns.text
};
define block .ram.data with fixed order{ section .data*,
section DATA,
section .ram.otg.data.a,
section .iar.init_table,
//section .mdns.data
};
define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
define block .ram.bss with fixed order{ section .bss*,
section .ssl_ram_map,
section .hal.flash.data*,
section .hal.gpio.data*,
section COMMON,
section .bdsram.data*,
section .bss* object heap_5.o
};
define block .bf_data with fixed order{ section .bfsram.data* };
define block .heap with fixed order{ section .heap* };
define block .stack_dummy with fixed order { section .stack };
place at start of BD_RAM_region { readwrite,
block IMAGE2,
//block IMAGE1_DBG,
block .ram.bss,
//block .bf_data,
};
//place at address mem:0x10052b00 { readwrite,
place at end of BD_RAM_region { readwrite,
block .bf_data,
};
define block SDRAM with fixed order{ section .sdram.text*,
section .sdram.data*,
section .mdns.text*,
section .mdns.data*,
section .text object HomeKit*,
section .text object fe_*,
section .text object ge_*,
section .text object sc_*,
section .text object auth_poly1305_donna.o,
section .text object sc_muladd.o
};
place at start of SDRAM_RAM_region { readwrite,
block SDRAM,
//block IMAGE1_DBG
};
/* TCM placement */
define overlay TCM_overlay { section .tcm.heap,
section .tcm.bss,
section .bss object memp.o,
block .heap,
block .stack_dummy
};
/* dummy code placement */
define overlay TCM_overlay { block IMAGE1_DBG };
place at start of TCM_region { readwrite,
overlay TCM_overlay
};
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library

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/**
******************************************************************************
* @file platform.c
* @author William Xu
* @version V1.0.0
* @date 05-May-2014
* @brief This file provides all MICO Peripherals mapping table and platform
* specific functions.
******************************************************************************
*
* The MIT License
* Copyright (c) 2014 MXCHIP Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
* IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
******************************************************************************
*/
#include "mico_platform.h"
#include "platform.h"
#include "platform_config.h"
#include "platform_peripheral.h"
#include "platform_config.h"
#include "platform_logging.h"
#include "wlan_platform_common.h"
#include "CheckSumUtils.h"
#include "keypad/gpio_button/button.h"
#ifdef USE_MiCOKit_EXT
#include "MiCOKit_EXT/micokit_ext.h"
#endif
/******************************************************
* Macros
******************************************************/
/******************************************************
* Constants
******************************************************/
/******************************************************
* Enumerations
******************************************************/
/******************************************************
* Type Definitions
******************************************************/
/******************************************************
* Structures
******************************************************/
/******************************************************
* Function Declarations
******************************************************/
extern WEAK void PlatformEasyLinkButtonClickedCallback(void);
extern WEAK void PlatformStandbyButtonClickedCallback(void);
extern WEAK void PlatformEasyLinkButtonLongPressedCallback(void);
extern WEAK void bootloader_start(void);
extern bool mfg_test_for_app (void);
/******************************************************
* Variables Definitions
******************************************************/
static uint32_t _default_start_time = 0;
static mico_timer_t _button_EL_timer;
const platform_gpio_t platform_gpio_pins[] =
{
/* Common GPIOs for internal use */
[MICO_SYS_LED] = { .pin = PB_2, },
//[MICO_RF_LED] = { .pin = PA_5, }, //MICO_GPIO_16
[BOOT_SEL] = { .pin = PC_4,}, //MICO_GPIO_16
[MFG_SEL] = { .pin = PC_5,}, //MICO_GPIO_30
[EasyLink_BUTTON] = { .pin = PB_3,}, //MICO_GPIO_11
/* GPIOs for external use */
[MICO_GPIO_12] = { .pin = PC_0, },
[MICO_GPIO_13] = { .pin = PC_3, },
[MICO_GPIO_14] = { .pin = PC_2, },
[MICO_GPIO_15] = { .pin = PC_1, },
[MICO_GPIO_19] = { .pin = PC_4, },
[MICO_GPIO_20] = { .pin = PC_5, },
};
/*
* Possible compile time inputs:
* - Set which ADC peripheral to use for each ADC. All on one ADC allows sequential conversion on all inputs. All on separate ADCs allows concurrent conversion.
*/
/* TODO : These need fixing */
const platform_adc_t platform_adc_peripherals[] =
{
[MICO_ADC_1] =
{
.pin = AD_1,
},
[MICO_ADC_2] =
{
.pin = AD_2,
},
[MICO_ADC_3] =
{
.pin = AD_3,
},
};
/* PWM mappings */
const platform_pwm_t platform_pwm_peripherals[] =
{
[MICO_PWM_1] =
{
.pin = PC_0,
},
[MICO_PWM_2] =
{
.pin = PC_1,
},
[MICO_PWM_3] =
{
.pin = PC_2,
},
[MICO_PWM_4] =
{
.pin = PC_3,
},
/* TODO: fill in the other options here ... */
};
const platform_spi_t platform_spi_peripherals[] =
{
[MICO_SPI_1] =
{
.mosi = PC_2,
.miso = PC_3,
.sclk = PC_1,
.ssel = PC_0,
},
};
platform_uart_driver_t platform_spi_drivers[MICO_UART_MAX];
const platform_uart_t platform_uart_peripherals[] =
{
[MICO_UART_1] =
{
.tx = PA_7,
.rx = PA_6,
},
};
platform_uart_driver_t platform_uart_drivers[MICO_UART_MAX];
const platform_i2c_t platform_i2c_peripherals[] =
{
[MICO_I2C_1] =
{
.sda = PB_3,
.scl = PB_2,
},
};
platform_i2c_driver_t platform_i2c_drivers[MICO_I2C_MAX];
/* Flash memory devices */
const platform_flash_t platform_flash_peripherals[] =
{
[MICO_FLASH_SPI] =
{
.flash_type = FLASH_TYPE_SPI,
.flash_start_addr = 0x00000000,
.flash_length = 0x200000,
.flash_readonly_start = 0x9000,
.flash_readonly_len = 0x2000,
},
};
platform_flash_driver_t platform_flash_drivers[MICO_FLASH_MAX];
#if 1
/* Logic partition on flash devices */
const mico_logic_partition_t mico_partitions[] =
{
[MICO_PARTITION_BOOTLOADER] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "Bootloader",
.partition_start_addr = 0xB000,
.partition_length = 0x8000, //32k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_DIS,
},
[MICO_PARTITION_APPLICATION] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "Application",
.partition_start_addr = 0x13000,
.partition_length = 0x90000, //576k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[MICO_PARTITION_RF_FIRMWARE] =
{
.partition_owner = MICO_FLASH_NONE,
},
[MICO_PARTITION_FILESYS] =
{
.partition_owner = MICO_FLASH_NONE,
},
[MICO_PARTITION_PARAMETER_1] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "PARAMETER1",
.partition_start_addr = 0x000E0000,
.partition_length = 0x4000, // 16k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[MICO_PARTITION_PARAMETER_2] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "PARAMETER2",
.partition_start_addr = 0x000E4000,
.partition_length = 0x4000, //16k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[MICO_PARTITION_ATE] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "ATE",
.partition_start_addr = 0x00100000,
.partition_length = 0x60000, //384k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
[MICO_PARTITION_OTA_TEMP] =
{
.partition_owner = MICO_FLASH_SPI,
.partition_description = "OTA Storage",
.partition_start_addr = 0x00160000,
.partition_length = 0x90000, //576k bytes
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
#endif
/******************************************************
* Interrupt Handler Definitions
******************************************************/
/******************************************************
* Function Definitions
******************************************************/
bool watchdog_check_last_reset( void )
{
#if 0
if ( RCC->CSR & RCC_CSR_WDGRSTF )
{
/* Clear the flag and return */
RCC->CSR |= RCC_CSR_RMVF;
return true;
}
#endif
return false;
}
void platform_init_peripheral_irq_priorities( void )
{
#if 0
/* Interrupt priority setup. Called by WICED/platform/MCU/STM32F2xx/platform_init.c */
NVIC_SetPriority( RTC_WKUP_IRQn , 1 ); /* RTC Wake-up event */
NVIC_SetPriority( SDIO_IRQn , 2 ); /* WLAN SDIO */
NVIC_SetPriority( DMA2_Stream3_IRQn, 3 ); /* WLAN SDIO DMA */
NVIC_SetPriority( DMA1_Stream3_IRQn, 3 ); /* WLAN SPI DMA */
NVIC_SetPriority( USART1_IRQn , 6 ); /* MICO_UART_1 */
NVIC_SetPriority( USART6_IRQn , 6 ); /* MICO_UART_2 */
NVIC_SetPriority( DMA2_Stream7_IRQn, 7 ); /* MICO_UART_1 TX DMA */
NVIC_SetPriority( DMA2_Stream2_IRQn, 7 ); /* MICO_UART_1 RX DMA */
NVIC_SetPriority( DMA2_Stream6_IRQn, 7 ); /* MICO_UART_2 TX DMA */
NVIC_SetPriority( DMA2_Stream1_IRQn, 7 ); /* MICO_UART_2 RX DMA */
NVIC_SetPriority( EXTI0_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI1_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI2_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI3_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI4_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI9_5_IRQn , 14 ); /* GPIO */
NVIC_SetPriority( EXTI15_10_IRQn , 14 ); /* GPIO */
#endif
}
void init_platform( void )
{
button_init_t init;
MicoGpioInitialize( (mico_gpio_t)MICO_SYS_LED, OUTPUT_PUSH_PULL );
MicoGpioOutputLow( (mico_gpio_t)MICO_SYS_LED );
MicoGpioInitialize( (mico_gpio_t)MICO_RF_LED, OUTPUT_OPEN_DRAIN_NO_PULL );
MicoGpioOutputHigh( (mico_gpio_t)MICO_RF_LED );
MicoGpioInitialize((mico_gpio_t)BOOT_SEL, INPUT_PULL_UP);
MicoGpioInitialize((mico_gpio_t)MFG_SEL, INPUT_PULL_UP);
init.gpio = EasyLink_BUTTON;
init.pressed_func = PlatformEasyLinkButtonClickedCallback;
init.long_pressed_func = PlatformEasyLinkButtonLongPressedCallback;
init.long_pressed_timeout = RestoreDefault_TimeOut;
button_init( IOBUTTON_EASYLINK, init );
/* Initialise RTC */
platform_rtc_init( );
}
#ifndef STDIO_BUFFER_SIZE
#define STDIO_BUFFER_SIZE 64
#endif
#ifndef MICO_DISABLE_STDIO
static const mico_uart_config_t stdio_uart_config =
{
.baud_rate = STDIO_UART_BAUDRATE,
.data_width = DATA_WIDTH_8BIT,
.parity = NO_PARITY,
.stop_bits = STOP_BITS_1,
.flow_control = FLOW_CONTROL_DISABLED,
.flags = 0,
};
static volatile ring_buffer_t stdio_rx_buffer;
static volatile uint8_t stdio_rx_data[STDIO_BUFFER_SIZE];
#endif /* #ifndef MICO_DISABLE_STDIO */
void init_platform_bootloader( void )
{
ring_buffer_init ( (ring_buffer_t*)&stdio_rx_buffer, (uint8_t*)stdio_rx_data, STDIO_BUFFER_SIZE );
platform_uart_init( &platform_uart_drivers[STDIO_UART], &platform_uart_peripherals[STDIO_UART], &stdio_uart_config, (ring_buffer_t*)&stdio_rx_buffer );
MicoGpioInitialize(BOOT_SEL, INPUT_PULL_UP);
MicoGpioInitialize(MFG_SEL, INPUT_PULL_UP);
MicoGpioInitialize( (mico_gpio_t)EasyLink_BUTTON, INPUT_PULL_UP );
}
void MicoSysLed(bool onoff)
{
if (onoff) {
MicoGpioOutputLow( (mico_gpio_t)MICO_SYS_LED );
} else {
MicoGpioOutputHigh( (mico_gpio_t)MICO_SYS_LED );
}
}
void MicoRfLed(bool onoff)
{
if (onoff) {
MicoGpioOutputLow( (mico_gpio_t)MICO_RF_LED );
} else {
MicoGpioOutputHigh( (mico_gpio_t)MICO_RF_LED );
}
}
static bool mfg_test_for_app (void)
{
mico_uart_config_t uart_config;
ring_buffer_t rx_buffer;
uint8_t * rx_data;
int ret = false;
int i,j;
uint8_t c;
rx_data = malloc (1024);
require (rx_data, exit);
/* Initialize UART interface */
uart_config.baud_rate = 921600;
uart_config.data_width = DATA_WIDTH_8BIT;
uart_config.parity = NO_PARITY;
uart_config.stop_bits = STOP_BITS_1;
uart_config.flow_control = FLOW_CONTROL_DISABLED;
uart_config.flags = UART_WAKEUP_DISABLE;
ring_buffer_init ((ring_buffer_t *)&rx_buffer, (uint8_t *)rx_data, 1024);
MicoUartInitialize (MFG_TEST, &uart_config, (ring_buffer_t *)&rx_buffer);
for(i=0, j=0;i<20;i++) {
if (kNoErr != MicoUartRecv( MFG_TEST, &c, 1, 10))
continue;
if (c == '#') {
j++;
if (j > 3) {
ret = true;
break;
}
} else {
ret = false;
break;
}
}
MicoUartFinalize(MFG_TEST);
free(rx_data);
exit:
return ret;
}
bool MicoShouldEnterMFGMode(void)
{
if(MicoGpioInputGet((mico_gpio_t)BOOT_SEL)==false && MicoGpioInputGet((mico_gpio_t)MFG_SEL)==false)
return true;
else {
#ifndef BOOTLOADER
if (mfg_test_for_app()) {
return true;
}
#endif
return false;
}
}
bool MicoShouldEnterBootloader(void)
{
if(MicoGpioInputGet((mico_gpio_t)BOOT_SEL)==false && MicoGpioInputGet((mico_gpio_t)MFG_SEL)==true)
return true;
else
return false;
}
bool MicoShouldEnterATEMode(void)
{
if(MicoGpioInputGet((mico_gpio_t)BOOT_SEL)==false && MicoGpioInputGet((mico_gpio_t)EasyLink_BUTTON)==false)
return true;
else
return false;
}
static int boot_blink_led = 0;
void ymodem_upload_done(void)
{
boot_blink_led = 1;
MicoGpioInitialize( (mico_gpio_t)MICO_SYS_LED, OUTPUT_PUSH_PULL );
}
void platform_bootloader_tick(void)
{
static int led_state = 0;
if (boot_blink_led == 0)
return;
if (led_state == 1) {
MicoSysLed(1);
led_state = 0;
} else {
MicoSysLed(0);
led_state = 1;
}
}

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@@ -0,0 +1,223 @@
/**
******************************************************************************
* @file platform.h
* @author William Xu
* @version V1.0.0
* @date 05-May-2014
* @brief This file provides all MICO Peripherals defined for current platform.
******************************************************************************
*
* The MIT License
* Copyright (c) 2014 MXCHIP Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
* IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
******************************************************************************
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Macros
******************************************************/
/******************************************************
* Constants
******************************************************/
/******************************************************
* Enumerations
******************************************************/
#define MICO_UNUSED 0xFF
typedef enum
{
MICO_SYS_LED,
//MICO_RF_LED,
BOOT_SEL,
MFG_SEL,
EasyLink_BUTTON,
MICO_GPIO_1 ,
MICO_GPIO_2,
MICO_GPIO_3,
MICO_GPIO_4,
MICO_GPIO_5,
MICO_GPIO_6,
MICO_GPIO_7,
MICO_GPIO_8,
MICO_GPIO_9,
MICO_GPIO_10,
MICO_GPIO_11,
MICO_GPIO_12,
MICO_GPIO_13,
MICO_GPIO_14,
MICO_GPIO_15,
MICO_GPIO_16,
MICO_GPIO_17,
MICO_GPIO_18,
MICO_GPIO_19,
MICO_GPIO_20,
MICO_GPIO_21,
MICO_GPIO_22,
MICO_GPIO_23,
MICO_GPIO_24,
MICO_GPIO_25,
MICO_GPIO_MAX, /* Denotes the total number of GPIO port aliases. Not a valid GPIO alias */
MICO_GPIO_NONE,
} mico_gpio_t;
typedef enum
{
MICO_SPI_1,
MICO_SPI_MAX, /* Denotes the total number of SPI port aliases. Not a valid SPI alias */
MICO_SPI_NONE,
} mico_spi_t;
typedef enum
{
MICO_I2C_1,
MICO_I2C_MAX, /* Denotes the total number of I2C port aliases. Not a valid I2C alias */
MICO_I2C_NONE,
} mico_i2c_t;
typedef enum
{
MICO_IIS_MAX, /* Denotes the total number of IIS port aliases. Not a valid IIS alias */
MICO_IIS_NONE,
} mico_iis_t;
typedef enum
{
MICO_PWM_1,
MICO_PWM_2,
MICO_PWM_3,
MICO_PWM_4,
MICO_PWM_MAX, /* Denotes the total number of PWM port aliases. Not a valid PWM alias */
MICO_PWM_NONE,
} mico_pwm_t;
typedef enum
{
MICO_ADC_1,
MICO_ADC_2,
MICO_ADC_3,
MICO_ADC_MAX, /* Denotes the total number of ADC port aliases. Not a valid ADC alias */
MICO_ADC_NONE,
} mico_adc_t;
typedef enum
{
MICO_UART_1,
MICO_UART_MAX, /* Denotes the total number of UART port aliases. Not a valid UART alias */
MICO_UART_NONE,
} mico_uart_t;
typedef enum
{
MICO_FLASH_EMBEDDED,
MICO_FLASH_SPI,
MICO_FLASH_MAX,
MICO_FLASH_NONE,
} mico_flash_t;
typedef enum
{
MICO_PARTITION_FILESYS,
MICO_PARTITION_USER_MAX
} mico_user_partition_t;
#ifdef BOOTLOADER
#define STDIO_UART MICO_UART_1
#define STDIO_UART_BAUDRATE (921600)
#else
#define STDIO_UART MICO_UART_NONE
#define STDIO_UART_BAUDRATE (115200)
#endif
#define UART_FOR_APP MICO_UART_1
#define MFG_TEST MICO_UART_1
#define MFG_BAUDRATE 921600
#define CLI_UART MICO_UART_2
/* Components connected to external I/Os*/
#define Standby_SEL (MICO_GPIO_NONE)
#define MICO_RF_LED (MICO_GPIO_NONE)
/* I/O connection <-> Peripheral Connections */
#define MICO_I2C_CP (MICO_I2C_1)
#define USE_MICO_SPI_FLASH
#define MICO_FLASH_FOR_PARA MICO_FLASH_SPI
#define PARA_START_ADDRESS (uint32_t)0x00000000
#define PARA_END_ADDRESS (uint32_t)0x00000FFF
#define PARA_FLASH_SIZE (PARA_END_ADDRESS - PARA_START_ADDRESS + 1) /* 4k bytes*/
/* Arduino extention connector */
#define Arduino_RXD (MICO_GPIO_NONE)
#define Arduino_TXD (MICO_GPIO_NONE)
#define Arduino_D2 (MICO_GPIO_NONE)
#define Arduino_D3 (MICO_GPIO_NONE)
#define Arduino_D4 (MICO_GPIO_NONE)
#define Arduino_D5 (MICO_GPIO_NONE)
#define Arduino_D6 (MICO_GPIO_NONE)
#define Arduino_D7 (MICO_GPIO_NONE)
//
#define Arduino_D8 (MICO_GPIO_NONE)
#define Arduino_D9 (MICO_GPIO_NONE)
#define Arduino_CS (MICO_GPIO_NONE)//(MICO_GPIO_12)
#define Arduino_SI (MICO_GPIO_NONE)//(MICO_GPIO_14)
#define Arduino_SO (MICO_GPIO_NONE)//(MICO_GPIO_13)
#define Arduino_SCK (MICO_GPIO_NONE)//(MICO_GPIO_15)
#define Arduino_SDA (MICO_GPIO_19)
#define Arduino_SCL (MICO_GPIO_20)
//
#define Arduino_A0 (MICO_ADC_NONE)
#define Arduino_A1 (MICO_ADC_NONE)
#define Arduino_A2 (MICO_ADC_NONE)
#define Arduino_A3 (MICO_ADC_NONE)
#define Arduino_A4 (MICO_ADC_NONE)
#define Arduino_A5 (MICO_ADC_NONE)
//
#define Arduino_I2C (MICO_SPI_NONE)
#define Arduino_SPI (MICO_SPI_NONE)
#define Arduino_UART (MICO_UART_1)
#ifdef USE_MiCOKit_EXT
#define MICO_I2C_CP (Arduino_I2C)
#include "MiCOKit_EXT/micokit_ext_def.h"
#else
#define MICO_I2C_CP (MICO_I2C_NONE)
#endif //USE_MiCOKit_EXT
#ifdef __cplusplus
} /*extern "C" */
#endif

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@@ -0,0 +1,174 @@
/*
* Automatically generated by make menuconfig: don't edit
*/
#define AUTOCONF_INCLUDED
/*
* Target Platform Selection
*/
#define CONFIG_WITHOUT_MONITOR 1
#define CONFIG_BOOT_TO_UPGRADE_IMG2 1
#define CONFIG_RTL8195A 1
#undef CONFIG_FPGA
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
#undef CONFIG_MP
#define RTL8195A 1
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_166_6MHZ 1
#undef CONFIG_CPU_83_3MHZ
#undef CONFIG_CPU_41_6MHZ
#undef CONFIG_CPU_20_8MHZ
#undef CONFIG_CPU_10_4MHZ
#undef CONFIG_CPU_4MHZ
#undef CONFIG_FPGA_CLK
#define PLATFORM_CLOCK (166666666)
#define CPU_CLOCK_SEL_VALUE (0)
#define CONFIG_SDR_CLK 1
#undef CONFIG_SDR_100MHZ
#define CONFIG_SDR_50MHZ 1
#undef CONFIG_SDR_25MHZ
#undef CONFIG_SDR_12_5MHZ
#define SDR_CLOCK_SEL_VALUE (1)
#define CONFIG_BOOT_PROCEDURE 1
#define CONFIG_BOOT_FROM_JTAG 1
#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE
#define CONFIG_KERNEL 1
#define PLATFORM_FREERTOS 1
#undef PLATFORM_UCOSII
#undef PLATFORM_ECOS
#undef CONFIG_TASK_SCHEDUL_DIS
#define TASK_SCHEDULER_DISABLED (0)
#define CONFIG_NORMALL_MODE 1
#undef CONFIG_MEMORY_VERIFY_MODE
#define CONFIG_TIMER_EN 1
#define CONFIG_TIMER_NORMAL 1
#undef CONFIG_TIMER_TEST
#define CONFIG_TIMER_MODULE 1
#define CONFIG_WDG 1
#undef CONFIG_WDG_NON
#define CONFIG_WDG_NORMAL 1
#define CONFIG_GDMA_EN 1
#define CONFIG_GDMA_NORMAL 1
#undef CONFIG_GDMA_TEST
#define CONFIG_GDMA_MODULE 1
#define CONFIG_WIFI_EN 1
#define CONFIG_WIFI_NORMAL 1
#undef CONFIG_WIFI_TEST
#define CONFIG_WIFI_MODULE 1
#define CONFIG_GPIO_EN 1
#define CONFIG_GPIO_NORMAL 1
#undef CONFIG_GPIO_TEST
#define CONFIG_GPIO_MODULE 1
#undef CONFIG_SDIO_DEVICE_EN
#undef CONFIG_SDIO_HOST_EN
#undef CONFIG_USB_EN
#define CONFIG_SPI_COM_EN 1
#define CONFIG_SPI_COM_NORMAL 1
#undef CONFIG_SPI_COM_TEST
#define CONFIG_SPI_COM_MODULE 1
#define CONFIG_UART_EN 1
#define CONFIG_UART_NORMAL 1
#undef CONFIG_UART_TEST
#define CONFIG_UART_MODULE 1
#define CONFIG_I2C_EN 1
#define CONFIG_I2C_NORMAL 1
#undef CONFIG_I2C_TEST
#define CONFIG_I2C_MODULE 1
#undef CONFIG_DEBUG_LOG_I2C_HAL
#undef CONFIG_PCM_EN
#define CONFIG_I2S_EN 1
#define CONFIG_I2S_NORMAL 1
#undef CONFIG_I2S_TEST
#define CONFIG_I2S_MODULE 1
#undef CONFIG_DEBUG_LOG_I2S_HAL
#define CONFIG_NFC_EN 1
#define CONFIG_NFC_NORMAL 1
#undef CONFIG_NFC_TEST
#define CONFIG_NFC_MODULE 1
#define CONFIG_SOC_PS_EN 1
#define CONFIG_SOC_PS_NORMAL 1
#undef CONFIG_SOC_PS_TEST
#define CONFIG_SOC_PS_MODULE 1
#define CONFIG_CRYPTO_EN 1
#define CONFIG_CRYPTO_NORMAL 1
#undef CONFIG_CRYPTO_TEST
#define CONFIG_CRYPTO_MODULE 1
#undef CONFIG_MII_EN
#define CONFIG_PWM_EN 1
#define CONFIG_PWM_NORMAL 1
#undef CONFIG_PWM_TEST
#define CONFIG_PWM_MODULE 1
#define CONFIG_EFUSE_EN 1
#define CONFIG_EFUSE_NORMAL 1
#undef CONFIG_EFUSE_TEST
#define CONFIG_EFUSE_MODULE 1
#define CONFIG_SDR_EN 1
#define CONFIG_SDR_NORMAL 1
#undef CONFIG_SDR_TEST
#define CONFIG_SDR_MODULE 1
#define CONFIG_SPIC_EN 1
#define CONFIG_SPIC_NORMAL 1
#undef CONFIG_SPIC_TEST
#define CONFIG_SPIC_MODULE 1
#define CONFIG_ADC_EN 1
#define CONFIG_DAC_EN 1
#define CONFIG_NOR_FLASH 1
#undef CONFIG_SPI_FLASH
#undef CONFIG_NAND_FLASH
#undef CONFIG_NONE_FLASH
/*
* Engineer Mode Config
*/
#undef CONFIG_JTAG
#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE
#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE
#undef CONFIG_CMSIS_MATH_LIB_EN
/*
* < Application Config
*/
#define CONFIG_NETWORK 1
#define CONFIG_RTLIB_EN 1
#define CONFIG_RTLIB_NORMAL 1
#undef CONFIG_RTLIB_TEST
#define CONFIG_RTLIB_MODULE 1
/*
* < System Debug Message Config
*/
#define CONFIG_UART_LOG_HISTORY 1
#undef CONFIG_CONSOLE_NORMALL_MODE
#define CONFIG_CONSOLE_VERIFY_MODE 1
#define CONFIG_DEBUG_LOG 1
#define CONFIG_DEBUG_ERR_MSG 1
#undef CONFIG_DEBUG_WARN_MSG
#undef CONFIG_DEBUG_INFO_MSG
/*
* < SDK Option Config
*/
#undef CONFIG_MBED_ENABLED
#undef CONFIG_APP_DEMO
/*
* < Select Chip Version
*/
#undef CONFIG_CHIP_A_CUT
#define CONFIG_CHIP_B_CUT 1
#undef CONFIG_CHIP_C_CUT
/*
* < Build Option
*/
#define CONFIG_LINK_ROM_LIB 1
#undef CONFIG_LINK_ROM_SYMB
#undef CONFIG_NORMAL_BUILD
#undef CONFIG_RELEASE_BUILD
#undef CONFIG_RELEASE_BUILD_LIBRARIES
#undef CONFIG_LIB_BUILD_RAM
#define CONFIG_RELEASE_BUILD_RAM_ALL 1
#undef CONFIG_IMAGE_ALL
#define CONFIG_IMAGE_SEPARATE 1

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@@ -0,0 +1,126 @@
/**
******************************************************************************
* @file platform_config.h
* @author William Xu
* @version V1.0.0
* @date 05-May-2014
* @brief This file provides common configuration for current platform.
******************************************************************************
*
* The MIT License
* Copyright (c) 2014 MXCHIP Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
* IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
******************************************************************************
*/
#ifndef __PLATFORM_COMMON_CONFIG_H__
#define __PLATFORM_COMMON_CONFIG_H__
#pragma once
/******************************************************
* Macros
******************************************************/
/******************************************************
* Constants
******************************************************/
#define HARDWARE_REVISION "3081"
#define DEFAULT_NAME "EMW3081 Module"
#define MODEL "EMW3081"
/* MICO RTOS tick rate in Hz */
#define MICO_DEFAULT_TICK_RATE_HZ (1000)
/************************************************************************
* Uncomment to disable watchdog. For debugging only */
//#define MICO_DISABLE_WATCHDOG
/************************************************************************
* Uncomment to disable standard IO, i.e. printf(), etc. */
//#define MICO_DISABLE_STDIO
/************************************************************************
* Uncomment to disable MCU powersave API functions */
#ifdef BOOTLOADER
#define MICO_DISABLE_MCU_POWERSAVE
#endif
/************************************************************************
* Uncomment to enable MCU real time clock */
#define MICO_ENABLE_MCU_RTC
/************************************************************************
* Restore default and start easylink after press down EasyLink button for 3 seconds. */
#define RestoreDefault_TimeOut (3000)
/************************************************************************
* Restore default and start easylink after press down EasyLink button for 3 seconds. */
#define MCU_CLOCK_HZ (120000000)
/************************************************************************
* How many bits are used in NVIC priority configuration */
#define CORTEX_NVIC_PRIO_BITS (4)
/************************************************************************
* Enable write protection to write-disabled embedded flash sectors */
//#define MCU_EBANLE_FLASH_PROTECT
/************************************************************************
* Uncomment to enable go to bootloader mode when stdio received many continuous spaces. */
#define MICO_ENABLE_STDIO_TO_BOOT
/************************************************************************
* Uncomment to enable MXCHIP MFG Test to output the CRC value of the firmware. */
#define MFG_TEST_PRINT_CRC
/************************************************************************
* Uncomment to enable Bootloader call user defined tick function. */
#define BOOTLOADER_USER_TICK
/******************************************************
* MCU Constants and Options
*
* NOTE: The clock configuration utility from ST is used to calculate these values
* http://www.st.com/st-web-ui/static/active/en/st_prod_software_internet/resource/technical/software/utility/stsw-stm32090.zip
******************************************************/
//#define MICO_USE_BUILTIN_RF_DRIVER
/******************************************************
* Enumerations
******************************************************/
/******************************************************
* Type Definitions
******************************************************/
/******************************************************
* Structures
******************************************************/
/******************************************************
* Global Variables
******************************************************/
/******************************************************
* Function Declarations
******************************************************/
#endif

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/**
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
/*For MP mode setting*/
#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode
#endif
/**
* For interactive mode configurations, depents on log service
*/
#if SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/******************************************************************************/
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_WEBSERVER 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 0
#define CONFIG_ENABLE_P2P 0//on/off p2p cmd in log_service or interactive mode
/* For WPS and P2P */
#define CONFIG_WPS
#if defined(CONFIG_WPS)
#define CONFIG_ENABLE_WPS 1
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
/*For fast reconnection*/
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#endif //end of #if CONFIG_WLAN
/*******************************************************************************/
/**
* For iNIC configurations
*/
#define CONFIG_INIC_EN 0//enable iNIC mode
#if CONFIG_INIC_EN
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 0
#define CONFIG_INIC_SDIO_HCI 1 //for SDIO or USB iNIC
#define CONFIG_INIC_USB_HCI 0
#endif
/*For google nest example, make sure the TCP is open*/
#define CONFIG_EXAMPLE_GOOGLE_NEST 0
/* For mDNS example */
#define CONFIG_EXAMPLE_MDNS 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For uart adapter example */
/* Please also configure LWIP_IGMP to 1 and LWIP_TCP_DELAY_DISABLE to 1
in lwip_opt.h for support uart adapter*/
#define CONFIG_EXAMPLE_UART_ADAPTER 0
#if CONFIG_EXAMPLE_UART_ADAPTER
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#undef CONFIG_EXAMPLE_MDNS
#define CONFIG_EXAMPLE_MDNS 1
#define LWIP_IGMP 1
#endif
#endif