mirror of
https://github.com/oopuuu/zTC1.git
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修复mico-sdk错误
This commit is contained in:
nhkefus
@@ -1,376 +1,376 @@
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/**
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******************************************************************************
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* @file platform_gpio.c
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provide GPIO driver functions.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "mico.h"
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#include "platform.h"
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#include "platform_peripheral.h"
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#include "platform_logging.h"
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/******************************************************
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* Constants
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******************************************************/
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#define PINS_PER_PORT (32) /* Px00 to Px31 */
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#define TOTAL_PORTS ( 2) /* PIOA to B */
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/******************************************************
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* Enumerations
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******************************************************/
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/******************************************************
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* Type Definitions
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******************************************************/
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/******************************************************
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* Structures
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******************************************************/
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/* Structure of runtime GPIO IRQ data */
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#pragma pack(1)
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typedef struct
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{
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bool wakeup_pin;
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platform_gpio_irq_callback_t callback;
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void* arg;
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} samg5x_gpio_irq_data_t;
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#pragma pack()
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/******************************************************
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* Variables Definitions
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******************************************************/
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/* Runtime GPIO IRQ data */
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static samg5x_gpio_irq_data_t gpio_irq_data[TOTAL_PORTS][PINS_PER_PORT];
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///* GPIO IRQ interrupt vectors */
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static const IRQn_Type irq_vectors[] =
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{
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[0] = PIOA_IRQn,
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[1] = PIOB_IRQn,
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};
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/******************************************************
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* Function Declarations
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******************************************************/
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/******************************************************
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* Function Definitions
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******************************************************/
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OSStatus platform_gpio_init( const platform_gpio_t* gpio, platform_pin_config_t config )
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{
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ioport_mode_t mode;
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enum ioport_direction direction;
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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switch ( config )
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{
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case INPUT_PULL_UP:
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{
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direction = IOPORT_DIR_INPUT;
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mode = IOPORT_MODE_PULLUP;
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break;
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}
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case INPUT_PULL_DOWN:
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{
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direction = IOPORT_DIR_INPUT;
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mode = IOPORT_MODE_PULLDOWN;
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break;
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}
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case INPUT_HIGH_IMPEDANCE:
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{
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direction = IOPORT_DIR_INPUT;
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mode = 0;
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break;
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}
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case OUTPUT_PUSH_PULL:
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{
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direction = IOPORT_DIR_OUTPUT;
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mode = 0;
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break;
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}
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case OUTPUT_OPEN_DRAIN_NO_PULL:
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{
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direction = IOPORT_DIR_OUTPUT;
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mode = IOPORT_MODE_OPEN_DRAIN;
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break;
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}
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case OUTPUT_OPEN_DRAIN_PULL_UP:
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{
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direction = IOPORT_DIR_OUTPUT;
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mode = IOPORT_MODE_OPEN_DRAIN | IOPORT_MODE_PULLUP;
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break;
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}
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default:
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{
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err = kParamErr;
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goto exit;
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}
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}
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ioport_enable_pin ( gpio->pin );
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ioport_set_pin_mode( gpio->pin, mode );
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ioport_set_pin_dir ( gpio->pin, direction );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_peripheral_pin_init( const platform_gpio_t* gpio, ioport_mode_t pin_mode )
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{
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable( );
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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/* Set pin mode and disable GPIO peripheral */
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ioport_set_pin_mode( gpio->pin, pin_mode );
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ioport_disable_pin( gpio->pin );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_deinit( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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ioport_disable_pin( gpio->pin );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_output_high( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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platform_mcu_powersave_disable();
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ioport_set_pin_level( gpio->pin, IOPORT_PIN_LEVEL_HIGH );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_output_low( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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platform_mcu_powersave_disable();
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ioport_set_pin_level( gpio->pin, IOPORT_PIN_LEVEL_LOW );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_output_trigger( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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platform_mcu_powersave_disable();
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ioport_toggle_pin_level( gpio->pin );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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bool platform_gpio_input_get( const platform_gpio_t* gpio )
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{
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bool result = false;
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platform_mcu_powersave_disable();
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require_quiet( gpio != NULL, exit);
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result = ( ioport_get_pin_level( gpio->pin ) == false ) ? false : true;
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exit:
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platform_mcu_powersave_enable();
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return result;
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}
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OSStatus platform_gpio_irq_enable( const platform_gpio_t* gpio, platform_gpio_irq_trigger_t trigger, platform_gpio_irq_callback_t handler, void* arg )
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{
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ioport_port_mask_t mask = ioport_pin_to_mask( gpio->pin );
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ioport_port_t port = ioport_pin_to_port_id( gpio->pin );
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volatile Pio* port_register = arch_ioport_port_to_base( port );
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uint8_t pin_number = (gpio->pin) & 0x1F;
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uint32_t temp;
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uint8_t samg5x_irq_trigger;
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OSStatus err = kNoErr;
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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NVIC_DisableIRQ( irq_vectors[port] );
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NVIC_ClearPendingIRQ( irq_vectors[port] );
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gpio_irq_data[port][pin_number].wakeup_pin = gpio->is_wakeup_pin;
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gpio_irq_data[port][pin_number].arg = arg;
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gpio_irq_data[port][pin_number].callback = handler;
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switch ( trigger )
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{
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case IRQ_TRIGGER_RISING_EDGE: samg5x_irq_trigger = IOPORT_SENSE_RISING; break;
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case IRQ_TRIGGER_FALLING_EDGE: samg5x_irq_trigger = IOPORT_SENSE_FALLING; break;
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case IRQ_TRIGGER_BOTH_EDGES: samg5x_irq_trigger = IOPORT_SENSE_BOTHEDGES; break;
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default:
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err = kParamErr;
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goto exit;
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}
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if( gpio->is_wakeup_pin == true )
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{
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platform_powersave_enable_wakeup_pin( gpio );
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}
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if ( samg5x_irq_trigger == IOPORT_SENSE_RISING || samg5x_irq_trigger == IOPORT_SENSE_BOTHEDGES )
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{
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port_register->PIO_AIMER |= mask;
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port_register->PIO_ESR |= mask;
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port_register->PIO_REHLSR |= mask;
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}
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if ( samg5x_irq_trigger == IOPORT_SENSE_FALLING || samg5x_irq_trigger == IOPORT_SENSE_BOTHEDGES )
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{
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port_register->PIO_AIMER |= mask;
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port_register->PIO_ESR |= mask;
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port_register->PIO_FELLSR |= mask;
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}
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/* Read ISR to clear residual interrupt status */
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temp = port_register->PIO_ISR;
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UNUSED_PARAMETER( temp );
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/* Enable interrupt source */
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port_register->PIO_IER |= mask;
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NVIC_EnableIRQ( irq_vectors[port] );
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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OSStatus platform_gpio_irq_disable( const platform_gpio_t* gpio )
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{
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OSStatus err = kNoErr;
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ioport_port_mask_t mask = ioport_pin_to_mask ( gpio->pin );
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ioport_port_t port = ioport_pin_to_port_id( gpio->pin );
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volatile Pio* port_register = arch_ioport_port_to_base( port );
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platform_mcu_powersave_disable();
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
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/* Disable interrupt on pin */
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port_register->PIO_IDR = mask;
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/* Disable Cortex-M interrupt vector as well if no pin interrupt is enabled */
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if ( port_register->PIO_IMR == 0 )
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{
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NVIC_DisableIRQ( irq_vectors[port] );
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}
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gpio_irq_data[port][mask].wakeup_pin = false;
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gpio_irq_data[port][mask].arg = 0;
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gpio_irq_data[port][mask].callback = NULL;
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exit:
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platform_mcu_powersave_enable();
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return err;
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}
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/******************************************************
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* STM32F2xx Internal Function Definitions
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******************************************************/
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OSStatus platform_gpio_irq_manager_init( void )
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{
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memset( &gpio_irq_data, 0, sizeof( gpio_irq_data ) );
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return kNoErr;
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}
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/******************************************************
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* IRQ Handler Definitions
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******************************************************/
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void gpio_irq( ioport_port_t port )
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{
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volatile Pio* port_register = arch_ioport_port_to_base( port );
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uint32_t status = port_register->PIO_ISR; /* Get interrupt status. Read clears the interrupt */
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uint32_t mask = port_register->PIO_IMR;
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uint32_t iter = 0;
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if ( ( status != 0 ) && ( mask != 0 ) )
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{
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/* Call the respective GPIO interrupt handler/callback */
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for ( iter = 0; iter < PINS_PER_PORT; iter++, status >>= 1, mask >>= 1 )
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{
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if ( ( ( mask & 0x1 ) != 0 ) && ( ( status & 0x1 ) != 0 ) && ( gpio_irq_data[port][iter].callback != NULL ) )
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{
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if ( gpio_irq_data[port][iter].wakeup_pin == true )
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{
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platform_mcu_powersave_exit_notify();
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}
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gpio_irq_data[port][iter].callback( gpio_irq_data[port][iter].arg );
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}
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}
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}
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}
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/******************************************************
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* IRQ Handler Mapping
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******************************************************/
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MICO_RTOS_DEFINE_ISR( PIOA_Handler )
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{
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gpio_irq( (ioport_port_t)0 );
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}
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MICO_RTOS_DEFINE_ISR( PIOB_Handler )
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{
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gpio_irq( (ioport_port_t)1 );
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}
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MICO_RTOS_DEFINE_ISR( PIOC_Handler )
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{
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gpio_irq( (ioport_port_t)2 );
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}
|
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|
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/**
|
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******************************************************************************
|
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* @file platform_gpio.c
|
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* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
* @brief This file provide GPIO driver functions.
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
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|
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#include "mico.h"
|
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|
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#include "platform.h"
|
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#include "platform_peripheral.h"
|
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#include "platform_logging.h"
|
||||
|
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/******************************************************
|
||||
* Constants
|
||||
******************************************************/
|
||||
|
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#define PINS_PER_PORT (32) /* Px00 to Px31 */
|
||||
#define TOTAL_PORTS ( 2) /* PIOA to B */
|
||||
|
||||
/******************************************************
|
||||
* Enumerations
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Type Definitions
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Structures
|
||||
******************************************************/
|
||||
|
||||
/* Structure of runtime GPIO IRQ data */
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct
|
||||
{
|
||||
bool wakeup_pin;
|
||||
platform_gpio_irq_callback_t callback;
|
||||
void* arg;
|
||||
} samg5x_gpio_irq_data_t;
|
||||
#pragma pack()
|
||||
|
||||
|
||||
/******************************************************
|
||||
* Variables Definitions
|
||||
******************************************************/
|
||||
|
||||
/* Runtime GPIO IRQ data */
|
||||
static samg5x_gpio_irq_data_t gpio_irq_data[TOTAL_PORTS][PINS_PER_PORT];
|
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|
||||
///* GPIO IRQ interrupt vectors */
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||||
static const IRQn_Type irq_vectors[] =
|
||||
{
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||||
[0] = PIOA_IRQn,
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||||
[1] = PIOB_IRQn,
|
||||
};
|
||||
|
||||
/******************************************************
|
||||
* Function Declarations
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Function Definitions
|
||||
******************************************************/
|
||||
|
||||
OSStatus platform_gpio_init( const platform_gpio_t* gpio, platform_pin_config_t config )
|
||||
{
|
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ioport_mode_t mode;
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enum ioport_direction direction;
|
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OSStatus err = kNoErr;
|
||||
|
||||
platform_mcu_powersave_disable();
|
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require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
|
||||
switch ( config )
|
||||
{
|
||||
case INPUT_PULL_UP:
|
||||
{
|
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direction = IOPORT_DIR_INPUT;
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||||
mode = IOPORT_MODE_PULLUP;
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||||
break;
|
||||
}
|
||||
case INPUT_PULL_DOWN:
|
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{
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direction = IOPORT_DIR_INPUT;
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mode = IOPORT_MODE_PULLDOWN;
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break;
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||||
}
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case INPUT_HIGH_IMPEDANCE:
|
||||
{
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||||
direction = IOPORT_DIR_INPUT;
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||||
mode = 0;
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||||
break;
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||||
}
|
||||
case OUTPUT_PUSH_PULL:
|
||||
{
|
||||
direction = IOPORT_DIR_OUTPUT;
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||||
mode = 0;
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||||
break;
|
||||
}
|
||||
case OUTPUT_OPEN_DRAIN_NO_PULL:
|
||||
{
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||||
direction = IOPORT_DIR_OUTPUT;
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||||
mode = IOPORT_MODE_OPEN_DRAIN;
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||||
break;
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||||
}
|
||||
case OUTPUT_OPEN_DRAIN_PULL_UP:
|
||||
{
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||||
direction = IOPORT_DIR_OUTPUT;
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||||
mode = IOPORT_MODE_OPEN_DRAIN | IOPORT_MODE_PULLUP;
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||||
break;
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||||
}
|
||||
default:
|
||||
{
|
||||
err = kParamErr;
|
||||
goto exit;
|
||||
}
|
||||
}
|
||||
ioport_enable_pin ( gpio->pin );
|
||||
ioport_set_pin_mode( gpio->pin, mode );
|
||||
ioport_set_pin_dir ( gpio->pin, direction );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_peripheral_pin_init( const platform_gpio_t* gpio, ioport_mode_t pin_mode )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
platform_mcu_powersave_disable( );
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
|
||||
/* Set pin mode and disable GPIO peripheral */
|
||||
ioport_set_pin_mode( gpio->pin, pin_mode );
|
||||
ioport_disable_pin( gpio->pin );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_deinit( const platform_gpio_t* gpio )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
platform_mcu_powersave_disable();
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
|
||||
ioport_disable_pin( gpio->pin );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_output_high( const platform_gpio_t* gpio )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
platform_mcu_powersave_disable();
|
||||
|
||||
ioport_set_pin_level( gpio->pin, IOPORT_PIN_LEVEL_HIGH );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_output_low( const platform_gpio_t* gpio )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
platform_mcu_powersave_disable();
|
||||
|
||||
ioport_set_pin_level( gpio->pin, IOPORT_PIN_LEVEL_LOW );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_output_trigger( const platform_gpio_t* gpio )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
platform_mcu_powersave_disable();
|
||||
|
||||
ioport_toggle_pin_level( gpio->pin );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
bool platform_gpio_input_get( const platform_gpio_t* gpio )
|
||||
{
|
||||
bool result = false;
|
||||
|
||||
platform_mcu_powersave_disable();
|
||||
|
||||
require_quiet( gpio != NULL, exit);
|
||||
|
||||
result = ( ioport_get_pin_level( gpio->pin ) == false ) ? false : true;
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return result;
|
||||
}
|
||||
|
||||
OSStatus platform_gpio_irq_enable( const platform_gpio_t* gpio, platform_gpio_irq_trigger_t trigger, platform_gpio_irq_callback_t handler, void* arg )
|
||||
{
|
||||
ioport_port_mask_t mask = ioport_pin_to_mask( gpio->pin );
|
||||
ioport_port_t port = ioport_pin_to_port_id( gpio->pin );
|
||||
volatile Pio* port_register = arch_ioport_port_to_base( port );
|
||||
uint8_t pin_number = (gpio->pin) & 0x1F;
|
||||
uint32_t temp;
|
||||
uint8_t samg5x_irq_trigger;
|
||||
OSStatus err = kNoErr;
|
||||
|
||||
platform_mcu_powersave_disable();
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
|
||||
NVIC_DisableIRQ( irq_vectors[port] );
|
||||
NVIC_ClearPendingIRQ( irq_vectors[port] );
|
||||
|
||||
gpio_irq_data[port][pin_number].wakeup_pin = gpio->is_wakeup_pin;
|
||||
gpio_irq_data[port][pin_number].arg = arg;
|
||||
gpio_irq_data[port][pin_number].callback = handler;
|
||||
|
||||
switch ( trigger )
|
||||
{
|
||||
case IRQ_TRIGGER_RISING_EDGE: samg5x_irq_trigger = IOPORT_SENSE_RISING; break;
|
||||
case IRQ_TRIGGER_FALLING_EDGE: samg5x_irq_trigger = IOPORT_SENSE_FALLING; break;
|
||||
case IRQ_TRIGGER_BOTH_EDGES: samg5x_irq_trigger = IOPORT_SENSE_BOTHEDGES; break;
|
||||
default:
|
||||
err = kParamErr;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if( gpio->is_wakeup_pin == true )
|
||||
{
|
||||
platform_powersave_enable_wakeup_pin( gpio );
|
||||
}
|
||||
|
||||
if ( samg5x_irq_trigger == IOPORT_SENSE_RISING || samg5x_irq_trigger == IOPORT_SENSE_BOTHEDGES )
|
||||
{
|
||||
port_register->PIO_AIMER |= mask;
|
||||
port_register->PIO_ESR |= mask;
|
||||
port_register->PIO_REHLSR |= mask;
|
||||
}
|
||||
|
||||
if ( samg5x_irq_trigger == IOPORT_SENSE_FALLING || samg5x_irq_trigger == IOPORT_SENSE_BOTHEDGES )
|
||||
{
|
||||
port_register->PIO_AIMER |= mask;
|
||||
port_register->PIO_ESR |= mask;
|
||||
port_register->PIO_FELLSR |= mask;
|
||||
}
|
||||
|
||||
/* Read ISR to clear residual interrupt status */
|
||||
temp = port_register->PIO_ISR;
|
||||
UNUSED_PARAMETER( temp );
|
||||
|
||||
/* Enable interrupt source */
|
||||
port_register->PIO_IER |= mask;
|
||||
|
||||
NVIC_EnableIRQ( irq_vectors[port] );
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
OSStatus platform_gpio_irq_disable( const platform_gpio_t* gpio )
|
||||
{
|
||||
OSStatus err = kNoErr;
|
||||
ioport_port_mask_t mask = ioport_pin_to_mask ( gpio->pin );
|
||||
ioport_port_t port = ioport_pin_to_port_id( gpio->pin );
|
||||
volatile Pio* port_register = arch_ioport_port_to_base( port );
|
||||
|
||||
platform_mcu_powersave_disable();
|
||||
require_action_quiet( gpio != NULL, exit, err = kParamErr);
|
||||
|
||||
/* Disable interrupt on pin */
|
||||
port_register->PIO_IDR = mask;
|
||||
|
||||
/* Disable Cortex-M interrupt vector as well if no pin interrupt is enabled */
|
||||
if ( port_register->PIO_IMR == 0 )
|
||||
{
|
||||
NVIC_DisableIRQ( irq_vectors[port] );
|
||||
}
|
||||
|
||||
gpio_irq_data[port][mask].wakeup_pin = false;
|
||||
gpio_irq_data[port][mask].arg = 0;
|
||||
gpio_irq_data[port][mask].callback = NULL;
|
||||
|
||||
exit:
|
||||
platform_mcu_powersave_enable();
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************
|
||||
* STM32F2xx Internal Function Definitions
|
||||
******************************************************/
|
||||
OSStatus platform_gpio_irq_manager_init( void )
|
||||
{
|
||||
memset( &gpio_irq_data, 0, sizeof( gpio_irq_data ) );
|
||||
|
||||
return kNoErr;
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
* IRQ Handler Definitions
|
||||
******************************************************/
|
||||
|
||||
|
||||
void gpio_irq( ioport_port_t port )
|
||||
{
|
||||
volatile Pio* port_register = arch_ioport_port_to_base( port );
|
||||
uint32_t status = port_register->PIO_ISR; /* Get interrupt status. Read clears the interrupt */
|
||||
uint32_t mask = port_register->PIO_IMR;
|
||||
uint32_t iter = 0;
|
||||
|
||||
if ( ( status != 0 ) && ( mask != 0 ) )
|
||||
{
|
||||
/* Call the respective GPIO interrupt handler/callback */
|
||||
for ( iter = 0; iter < PINS_PER_PORT; iter++, status >>= 1, mask >>= 1 )
|
||||
{
|
||||
if ( ( ( mask & 0x1 ) != 0 ) && ( ( status & 0x1 ) != 0 ) && ( gpio_irq_data[port][iter].callback != NULL ) )
|
||||
{
|
||||
if ( gpio_irq_data[port][iter].wakeup_pin == true )
|
||||
{
|
||||
platform_mcu_powersave_exit_notify();
|
||||
}
|
||||
gpio_irq_data[port][iter].callback( gpio_irq_data[port][iter].arg );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
* IRQ Handler Mapping
|
||||
******************************************************/
|
||||
MICO_RTOS_DEFINE_ISR( PIOA_Handler )
|
||||
{
|
||||
gpio_irq( (ioport_port_t)0 );
|
||||
}
|
||||
|
||||
MICO_RTOS_DEFINE_ISR( PIOB_Handler )
|
||||
{
|
||||
gpio_irq( (ioport_port_t)1 );
|
||||
}
|
||||
|
||||
MICO_RTOS_DEFINE_ISR( PIOC_Handler )
|
||||
{
|
||||
gpio_irq( (ioport_port_t)2 );
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user