mirror of
https://github.com/oopuuu/zTC1.git
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修复mico-sdk错误
This commit is contained in:
nhkefus
File diff suppressed because it is too large
Load Diff
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Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,52 +1,52 @@
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/**
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******************************************************************************
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* @file crt0_EWARM.h
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* @author William Xu
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* @version V1.0.0
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||||
* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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||||
******************************************************************************
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||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
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||||
*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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#pragma section=".intvec"
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#pragma section=".intvec_RAM"
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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#ifdef BOOTLOADER
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/* Set the Vector Table base location at 0x20000000 */
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//*SCB_VTOR_ADDRESS = 0x20000000;
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec_RAM");
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#else
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec");
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init_clocks();
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init_memory();
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#endif
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return 1; /* return 1 to force memory init */
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}
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/**
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******************************************************************************
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* @file crt0_EWARM.h
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* @author William Xu
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||||
* @version V1.0.0
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||||
* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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#pragma section=".intvec"
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#pragma section=".intvec_RAM"
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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#ifdef BOOTLOADER
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/* Set the Vector Table base location at 0x20000000 */
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//*SCB_VTOR_ADDRESS = 0x20000000;
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec_RAM");
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#else
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec");
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init_clocks();
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init_memory();
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#endif
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return 1; /* return 1 to force memory init */
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}
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@@ -1,46 +1,46 @@
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/**
|
||||
******************************************************************************
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||||
* @file crt0_RVMDK.h
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* @author William Xu
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||||
* @version V1.0.0
|
||||
* @date 16-Sep-2014
|
||||
* @brief __low_level_init called by IAR before main.
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
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||||
|
||||
#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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extern unsigned long Image$$ER_IROM1$$Base;
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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int __low_level_init( void )
|
||||
{
|
||||
extern void init_clocks(void);
|
||||
extern void init_memory(void);
|
||||
/* IAR allows init functions in __low_level_init(), but it is run before global
|
||||
* variables have been initialised, so the following init still needs to be done
|
||||
* When using GCC, this is done in crt0_GCC.c
|
||||
*/
|
||||
|
||||
/* Setup the interrupt vectors address */
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||||
*SCB_VTOR_ADDRESS = (unsigned long)&Image$$ER_IROM1$$Base;
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init_clocks();
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init_memory();
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return 1; /* return 1 to force memory init */
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||||
}
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file crt0_RVMDK.h
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||||
* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 16-Sep-2014
|
||||
* @brief __low_level_init called by IAR before main.
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "platform.h"
|
||||
#include "crt0.h"
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||||
|
||||
extern void* app_hdr_start_addr_loc;
|
||||
#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
|
||||
#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
|
||||
|
||||
extern unsigned long Image$$ER_IROM1$$Base;
|
||||
|
||||
int __low_level_init( void );
|
||||
|
||||
/* This is the code that gets called on processor reset. To initialize the */
|
||||
/* device. */
|
||||
int __low_level_init( void )
|
||||
{
|
||||
extern void init_clocks(void);
|
||||
extern void init_memory(void);
|
||||
/* IAR allows init functions in __low_level_init(), but it is run before global
|
||||
* variables have been initialised, so the following init still needs to be done
|
||||
* When using GCC, this is done in crt0_GCC.c
|
||||
*/
|
||||
|
||||
/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long)&Image$$ER_IROM1$$Base;
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init_clocks();
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init_memory();
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return 1; /* return 1 to force memory init */
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}
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@@ -1,117 +1,117 @@
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/**
|
||||
******************************************************************************
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||||
* @file hardfault.c
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||||
* @author William Xu
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||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
* @brief This file provide debug information in hardfault.
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "stdio.h"
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#include "mico.h"
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#include "platform_config.h"
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extern OSStatus stdio_hardfault( char* data, uint32_t size );
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||||
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#if defined ( __CC_ARM )
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||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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||||
/* IAR iccarm specific functions */
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||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
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||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#include <cmsis_iar.h>
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#elif defined ( __GNUC__ )
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#endif
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void hard_fault_handler_c (unsigned int * hardfault_args)
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{
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unsigned int stacked_r0;
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unsigned int stacked_r1;
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unsigned int stacked_r2;
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||||
unsigned int stacked_r3;
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unsigned int stacked_r12;
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unsigned int stacked_lr;
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unsigned int stacked_pc;
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unsigned int stacked_psr;
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char logString[50];
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stacked_r0 = ((unsigned long) hardfault_args[0]);
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stacked_r1 = ((unsigned long) hardfault_args[1]);
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stacked_r2 = ((unsigned long) hardfault_args[2]);
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stacked_r3 = ((unsigned long) hardfault_args[3]);
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stacked_r12 = ((unsigned long) hardfault_args[4]);
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stacked_lr = ((unsigned long) hardfault_args[5]);
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stacked_pc = ((unsigned long) hardfault_args[6]);
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stacked_psr = ((unsigned long) hardfault_args[7]);
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sprintf (logString,"\n>>>>>>>>>>>>>>[");
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stdio_hardfault( logString, strlen(logString)+1 );
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switch(__get_IPSR())
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{
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case 3:
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sprintf (logString, "Hard Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 4:
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sprintf (logString, "Memory Manage");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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||||
|
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case 5:
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sprintf (logString, "Bus Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 6:
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sprintf (logString, "Usage Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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default:
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sprintf (logString, "Unknown Fault %ld", __get_IPSR());
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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}
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sprintf (logString, ",corrupt,dump registers]>>>>>>>>>>>>>>>>>>\n\r");
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R0 = 0x%08x\r\n", stacked_r0);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R1 = 0x%08x\r\n", stacked_r1);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R2 = 0x%08x\r\n", stacked_r2);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R3 = 0x%08x\r\n", stacked_r3);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R12 = 0x%08x\r\n", stacked_r12);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "LR [R14] = 0x%08x subroutine call return address\r\n", stacked_lr);
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stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "PC [R15] = 0x%08X program counter\r\n", stacked_pc);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "PSR = 0x%08X\r\n", stacked_psr);
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||||
stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "BFAR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED38))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "CFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED28))));
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stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "HFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
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||||
stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "DFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED30))));
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||||
stdio_hardfault( logString, strlen(logString)+1 );
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||||
sprintf (logString, "AFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
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||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
|
||||
while (1);
|
||||
}
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hardfault.c
|
||||
* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
* @brief This file provide debug information in hardfault.
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "stdio.h"
|
||||
#include "mico.h"
|
||||
#include "platform_config.h"
|
||||
|
||||
extern OSStatus stdio_hardfault( char* data, uint32_t size );
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
|
||||
#endif
|
||||
void hard_fault_handler_c (unsigned int * hardfault_args)
|
||||
{
|
||||
unsigned int stacked_r0;
|
||||
unsigned int stacked_r1;
|
||||
unsigned int stacked_r2;
|
||||
unsigned int stacked_r3;
|
||||
unsigned int stacked_r12;
|
||||
unsigned int stacked_lr;
|
||||
unsigned int stacked_pc;
|
||||
unsigned int stacked_psr;
|
||||
char logString[50];
|
||||
|
||||
stacked_r0 = ((unsigned long) hardfault_args[0]);
|
||||
stacked_r1 = ((unsigned long) hardfault_args[1]);
|
||||
stacked_r2 = ((unsigned long) hardfault_args[2]);
|
||||
stacked_r3 = ((unsigned long) hardfault_args[3]);
|
||||
|
||||
stacked_r12 = ((unsigned long) hardfault_args[4]);
|
||||
stacked_lr = ((unsigned long) hardfault_args[5]);
|
||||
stacked_pc = ((unsigned long) hardfault_args[6]);
|
||||
stacked_psr = ((unsigned long) hardfault_args[7]);
|
||||
|
||||
sprintf (logString,"\n>>>>>>>>>>>>>>[");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
switch(__get_IPSR())
|
||||
{
|
||||
case 3:
|
||||
sprintf (logString, "Hard Fault");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
break;
|
||||
|
||||
case 4:
|
||||
sprintf (logString, "Memory Manage");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
break;
|
||||
|
||||
case 5:
|
||||
sprintf (logString, "Bus Fault");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
break;
|
||||
|
||||
case 6:
|
||||
sprintf (logString, "Usage Fault");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
break;
|
||||
|
||||
default:
|
||||
sprintf (logString, "Unknown Fault %ld", __get_IPSR());
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
break;
|
||||
}
|
||||
sprintf (logString, ",corrupt,dump registers]>>>>>>>>>>>>>>>>>>\n\r");
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
|
||||
sprintf (logString, "R0 = 0x%08x\r\n", stacked_r0);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "R1 = 0x%08x\r\n", stacked_r1);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "R2 = 0x%08x\r\n", stacked_r2);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "R3 = 0x%08x\r\n", stacked_r3);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "R12 = 0x%08x\r\n", stacked_r12);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "LR [R14] = 0x%08x subroutine call return address\r\n", stacked_lr);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "PC [R15] = 0x%08X program counter\r\n", stacked_pc);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "PSR = 0x%08X\r\n", stacked_psr);
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "BFAR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED38))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "CFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED28))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "HFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "DFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED30))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
sprintf (logString, "AFSR = 0x%08lx\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
|
||||
stdio_hardfault( logString, strlen(logString)+1 );
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
0
mico-os/platform/Cortex-M4F/hardfault_handler.c
Executable file → Normal file
0
mico-os/platform/Cortex-M4F/hardfault_handler.c
Executable file → Normal file
@@ -1,88 +1,88 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file platform_assert.h
|
||||
* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/******************************************************
|
||||
* Macros
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Constants
|
||||
******************************************************/
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm__("bkpt")
|
||||
#elif defined ( __IAR_SYSTEMS_ICC__ )
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm("bkpt 0")
|
||||
#elif defined ( __CC_ARM )
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm("bkpt 0")
|
||||
#endif
|
||||
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
|
||||
#if defined ( __clang__ )
|
||||
|
||||
static inline /*@noreturn@*/void MICO_TRIGGER_BREAKPOINT( void ) __attribute__((analyzer_noreturn))
|
||||
{
|
||||
__asm__("bkpt");
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define MICO_TRIGGER_BREAKPOINT( ) do { __asm__("bkpt"); } while (0)
|
||||
|
||||
#endif /* #if defined ( __clang__ ) */
|
||||
|
||||
#ifdef NO_VECTORS
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm__("" : : : "memory"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm__("" : : : "memory"); } while (0)
|
||||
#else
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm__("CPSID i" : : : "memory"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm__("CPSIE i" : : : "memory"); } while (0)
|
||||
#endif
|
||||
|
||||
#define CSPR_INTERRUPTS_DISABLED (0x80)
|
||||
|
||||
#elif defined ( __IAR_SYSTEMS_ICC__ )
|
||||
|
||||
#define MICO_TRIGGER_BREAKPOINT() do { __asm("bkpt 0"); } while (0)
|
||||
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm("CPSID i"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm("CPSIE i"); } while (0)
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************
|
||||
* Enumerations
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Type Definitions
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Structures
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Global Variables
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Function Declarations
|
||||
******************************************************/
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file platform_assert.h
|
||||
* @author William Xu
|
||||
* @version V1.0.0
|
||||
* @date 05-May-2014
|
||||
******************************************************************************
|
||||
* UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
* Copyright (c) 2016 MXCHIP Inc.
|
||||
*
|
||||
* The contents of this file may not be disclosed to third parties, copied or
|
||||
* duplicated in any form, in whole or in part, without the prior written
|
||||
* permission of MXCHIP Corporation.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/******************************************************
|
||||
* Macros
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Constants
|
||||
******************************************************/
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm__("bkpt")
|
||||
#elif defined ( __IAR_SYSTEMS_ICC__ )
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm("bkpt 0")
|
||||
#elif defined ( __CC_ARM )
|
||||
#define MICO_ASSERTION_FAIL_ACTION() __asm("bkpt 0")
|
||||
#endif
|
||||
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
|
||||
#if defined ( __clang__ )
|
||||
|
||||
static inline /*@noreturn@*/void MICO_TRIGGER_BREAKPOINT( void ) __attribute__((analyzer_noreturn))
|
||||
{
|
||||
__asm__("bkpt");
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define MICO_TRIGGER_BREAKPOINT( ) do { __asm__("bkpt"); } while (0)
|
||||
|
||||
#endif /* #if defined ( __clang__ ) */
|
||||
|
||||
#ifdef NO_VECTORS
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm__("" : : : "memory"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm__("" : : : "memory"); } while (0)
|
||||
#else
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm__("CPSID i" : : : "memory"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm__("CPSIE i" : : : "memory"); } while (0)
|
||||
#endif
|
||||
|
||||
#define CSPR_INTERRUPTS_DISABLED (0x80)
|
||||
|
||||
#elif defined ( __IAR_SYSTEMS_ICC__ )
|
||||
|
||||
#define MICO_TRIGGER_BREAKPOINT() do { __asm("bkpt 0"); } while (0)
|
||||
|
||||
#define MICO_DISABLE_INTERRUPTS() do { __asm("CPSID i"); } while (0)
|
||||
#define MICO_ENABLE_INTERRUPTS() do { __asm("CPSIE i"); } while (0)
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************
|
||||
* Enumerations
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Type Definitions
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Structures
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Global Variables
|
||||
******************************************************/
|
||||
|
||||
/******************************************************
|
||||
* Function Declarations
|
||||
******************************************************/
|
||||
|
||||
0
mico-os/platform/Cortex-M4F/platform_core.c
Executable file → Normal file
0
mico-os/platform/Cortex-M4F/platform_core.c
Executable file → Normal file
Reference in New Issue
Block a user