mirror of
https://github.com/oopuuu/zTC1.git
synced 2025-12-15 22:48:14 +08:00
修复mico-sdk错误
This commit is contained in:
nhkefus
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,50 +1,50 @@
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/**
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******************************************************************************
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* @file crt0_EWARM.h
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* @author William Xu
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* @version V1.0.0
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* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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#pragma section=".intvec"
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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#ifdef BOOTLOADER
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/* Set the Vector Table base location at 0x20000000 */
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*SCB_VTOR_ADDRESS = 0x20000000;
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#else
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec");
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init_clocks();
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init_memory();
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#endif
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return 1; /* return 1 to force memory init */
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}
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/**
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******************************************************************************
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* @file crt0_EWARM.h
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* @author William Xu
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* @version V1.0.0
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* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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#pragma section=".intvec"
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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#ifdef BOOTLOADER
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/* Set the Vector Table base location at 0x20000000 */
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*SCB_VTOR_ADDRESS = 0x20000000;
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#else
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long )__section_begin(".intvec");
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init_clocks();
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init_memory();
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#endif
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return 1; /* return 1 to force memory init */
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}
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@@ -1,46 +1,46 @@
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/**
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******************************************************************************
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* @file crt0_IAR.h
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* @author William Xu
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* @version V1.0.0
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* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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extern unsigned long Image$$ER_IROM1$$Base;
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long)&Image$$ER_IROM1$$Base;
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init_clocks();
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init_memory();
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return 1; /* return 1 to force memory init */
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}
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/**
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******************************************************************************
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* @file crt0_IAR.h
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* @author William Xu
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* @version V1.0.0
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* @date 16-Sep-2014
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* @brief __low_level_init called by IAR before main.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "platform.h"
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#include "crt0.h"
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extern void* app_hdr_start_addr_loc;
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#define SCB_VTOR_ADDRESS ( ( volatile unsigned long* ) 0xE000ED08 )
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#define APP_HDR_START_ADDR ((unsigned char*)&app_hdr_start_addr_loc)
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extern unsigned long Image$$ER_IROM1$$Base;
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int __low_level_init( void );
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/* This is the code that gets called on processor reset. To initialize the */
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/* device. */
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int __low_level_init( void )
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{
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extern void init_clocks(void);
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extern void init_memory(void);
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/* IAR allows init functions in __low_level_init(), but it is run before global
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* variables have been initialised, so the following init still needs to be done
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* When using GCC, this is done in crt0_GCC.c
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*/
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/* Setup the interrupt vectors address */
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*SCB_VTOR_ADDRESS = (unsigned long)&Image$$ER_IROM1$$Base;
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init_clocks();
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init_memory();
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return 1; /* return 1 to force memory init */
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}
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@@ -1,118 +1,118 @@
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/**
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******************************************************************************
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* @file hardfault.c
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provide debug information in hardfault.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "stdio.h"
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#include "mico.h"
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#include "platform.h"
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extern OSStatus stdio_hardfault( char* data, uint32_t size );
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#if defined ( __CC_ARM )
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#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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/* IAR iccarm specific functions */
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#include <cmsis_iar.h>
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#elif defined ( __GNUC__ )
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#endif
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void hard_fault_handler_c (unsigned int * hardfault_args)
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{
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unsigned int stacked_r0;
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unsigned int stacked_r1;
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unsigned int stacked_r2;
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unsigned int stacked_r3;
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unsigned int stacked_r12;
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unsigned int stacked_lr;
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unsigned int stacked_pc;
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unsigned int stacked_psr;
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char logString[50];
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stacked_r0 = ((unsigned long) hardfault_args[0]);
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stacked_r1 = ((unsigned long) hardfault_args[1]);
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stacked_r2 = ((unsigned long) hardfault_args[2]);
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stacked_r3 = ((unsigned long) hardfault_args[3]);
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stacked_r12 = ((unsigned long) hardfault_args[4]);
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stacked_lr = ((unsigned long) hardfault_args[5]);
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stacked_pc = ((unsigned long) hardfault_args[6]);
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stacked_psr = ((unsigned long) hardfault_args[7]);
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sprintf (logString,"\n>>>>>>>>>>>>>>[");
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stdio_hardfault( logString, strlen(logString)+1 );
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switch(__get_IPSR())
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{
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case 3:
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sprintf (logString, "Hard Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 4:
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sprintf (logString, "Memory Manage");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 5:
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sprintf (logString, "Bus Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 6:
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sprintf (logString, "Usage Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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default:
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sprintf (logString, "Unknown Fault %d", __get_IPSR());
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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}
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sprintf (logString, ",corrupt,dump registers]>>>>>>>>>>>>>>>>>>\n\r");
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R0 = 0x08%x\r\n", stacked_r0);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R1 = 0x%08x\r\n", stacked_r1);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R2 = 0x%08x\r\n", stacked_r2);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R3 = 0x%08x\r\n", stacked_r3);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R12 = 0x%08x\r\n", stacked_r12);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "LR [R14] = 0x08%x subroutine call return address\r\n", stacked_lr);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "PC [R15] = 0x08%x program counter\r\n", stacked_pc);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "PSR = 0x08%x\r\n", stacked_psr);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "BFAR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED38))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "CFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED28))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "HFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "DFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED30))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "AFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
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stdio_hardfault( logString, strlen(logString)+1 );
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while (1);
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}
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/**
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******************************************************************************
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* @file hardfault.c
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* @author William Xu
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* @version V1.0.0
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* @date 05-May-2014
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* @brief This file provide debug information in hardfault.
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******************************************************************************
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* UNPUBLISHED PROPRIETARY SOURCE CODE
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* Copyright (c) 2016 MXCHIP Inc.
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*
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* The contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of MXCHIP Corporation.
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******************************************************************************
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*/
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#include "stdio.h"
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#include "mico.h"
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#include "platform.h"
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extern OSStatus stdio_hardfault( char* data, uint32_t size );
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#if defined ( __CC_ARM )
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#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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/* IAR iccarm specific functions */
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#include <cmsis_iar.h>
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#elif defined ( __GNUC__ )
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#endif
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void hard_fault_handler_c (unsigned int * hardfault_args)
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{
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unsigned int stacked_r0;
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unsigned int stacked_r1;
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unsigned int stacked_r2;
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unsigned int stacked_r3;
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unsigned int stacked_r12;
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unsigned int stacked_lr;
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unsigned int stacked_pc;
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unsigned int stacked_psr;
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char logString[50];
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stacked_r0 = ((unsigned long) hardfault_args[0]);
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stacked_r1 = ((unsigned long) hardfault_args[1]);
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stacked_r2 = ((unsigned long) hardfault_args[2]);
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stacked_r3 = ((unsigned long) hardfault_args[3]);
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stacked_r12 = ((unsigned long) hardfault_args[4]);
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stacked_lr = ((unsigned long) hardfault_args[5]);
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stacked_pc = ((unsigned long) hardfault_args[6]);
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stacked_psr = ((unsigned long) hardfault_args[7]);
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sprintf (logString,"\n>>>>>>>>>>>>>>[");
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stdio_hardfault( logString, strlen(logString)+1 );
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switch(__get_IPSR())
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{
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case 3:
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sprintf (logString, "Hard Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 4:
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sprintf (logString, "Memory Manage");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 5:
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sprintf (logString, "Bus Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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case 6:
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sprintf (logString, "Usage Fault");
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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default:
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sprintf (logString, "Unknown Fault %d", __get_IPSR());
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stdio_hardfault( logString, strlen(logString)+1 );
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break;
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}
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sprintf (logString, ",corrupt,dump registers]>>>>>>>>>>>>>>>>>>\n\r");
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R0 = 0x08%x\r\n", stacked_r0);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R1 = 0x%08x\r\n", stacked_r1);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R2 = 0x%08x\r\n", stacked_r2);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R3 = 0x%08x\r\n", stacked_r3);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "R12 = 0x%08x\r\n", stacked_r12);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "LR [R14] = 0x08%x subroutine call return address\r\n", stacked_lr);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "PC [R15] = 0x08%x program counter\r\n", stacked_pc);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "PSR = 0x08%x\r\n", stacked_psr);
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "BFAR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED38))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "CFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED28))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "HFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "DFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED30))));
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stdio_hardfault( logString, strlen(logString)+1 );
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sprintf (logString, "AFSR = 0x08%x\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
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stdio_hardfault( logString, strlen(logString)+1 );
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while (1);
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}
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0
mico-os/platform/Cortex-M3/hardfault_handler.c
Executable file → Normal file
0
mico-os/platform/Cortex-M3/hardfault_handler.c
Executable file → Normal file
0
mico-os/platform/Cortex-M3/platform_core.c
Executable file → Normal file
0
mico-os/platform/Cortex-M3/platform_core.c
Executable file → Normal file
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