mirror of
https://github.com/oopuuu/zTC1.git
synced 2025-12-16 23:18:24 +08:00
修复mico-sdk错误
This commit is contained in:
nhkefus
@@ -1,7 +1,7 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
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||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
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||||
@@ -1,14 +1,14 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
#
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# default ports
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telnet_port 4444
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gdb_port 3333
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gdb_memory_map enable
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init
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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#
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||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
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||||
# permission of MXCHIP Corporation.
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||||
#
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||||
# default ports
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telnet_port 4444
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gdb_port 3333
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gdb_memory_map enable
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init
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@@ -1,15 +1,15 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
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||||
# permission of MXCHIP Corporation.
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||||
#
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# Segger J-Link
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#
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# http://www.segger.com/jlink.html
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#
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interface jlink
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#
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# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
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||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
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# permission of MXCHIP Corporation.
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#
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# Segger J-Link
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#
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# http://www.segger.com/jlink.html
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#
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interface jlink
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0
mico-os/makefiles/OpenOCD/interface/swj-dp.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/interface/swj-dp.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/mem_helper.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/mem_helper.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/memory.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/memory.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/mmr_helpers.tcl
Executable file → Normal file
0
mico-os/makefiles/OpenOCD/mmr_helpers.tcl
Executable file → Normal file
@@ -1,12 +1,12 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
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||||
# permission of MXCHIP Corporation.
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||||
#
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# default ports
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reset
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#
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# UNPUBLISHED PROPRIETARY SOURCE CODE
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||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
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||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
#
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# default ports
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reset
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halt
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@@ -1,14 +1,14 @@
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#
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# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
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telnet_port 4444
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gdb_port 3333
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gdb_memory_map enable
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init
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||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
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gdb_port 3333
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gdb_memory_map enable
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init
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@@ -1,24 +1,24 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
#
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init
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#jtag_khz 100
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reset halt
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poll off
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#jtag_khz 1000
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# setup STM32 pll
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mww 0x40022000 0x32
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mww 0x40021004 0x3c0400
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mww 0x40021000 0x01000883
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sleep 10
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mww 0x40021004 0x3c0402
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sleep 10
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#
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# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
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||||
# The contents of this file may not be disclosed to third parties, copied or
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||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
#
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init
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#jtag_khz 100
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reset halt
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poll off
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#jtag_khz 1000
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# setup STM32 pll
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mww 0x40022000 0x32
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mww 0x40021004 0x3c0400
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mww 0x40021000 0x01000883
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sleep 10
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mww 0x40021004 0x3c0402
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sleep 10
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jtag_khz 6000
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@@ -1,92 +1,92 @@
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#
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||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
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||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
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||||
#
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# script for stm32
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source [find mico-os/makefiles/OpenOCD/interface/swj-dp.tcl]
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source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]
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set CHIP_FLASH_START 0x08000000
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set CHIP_RAM_START 0x20000000
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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adapter_khz 1000
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0008
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# Section 26.6.3
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set _CPUTAPID 0x3ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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# FIXME this never gets used to override defaults...
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0008
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# Section 29.6.2
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# Low density devices, Rev A
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set _BSTAPID1 0x06412041
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# Medium density devices, Rev A
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set _BSTAPID2 0x06410041
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# Medium density devices, Rev B and Rev Z
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set _BSTAPID3 0x16410041
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set _BSTAPID4 0x06420041
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# High density devices, Rev A
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set _BSTAPID5 0x06414041
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# Connectivity line devices, Rev A and Rev Z
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set _BSTAPID6 0x06418041
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# XL line devices, Rev A
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set _BSTAPID7 0x06430041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
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-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
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-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
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-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys $CHIP_RAM_START -work-area-size $_WORKAREASIZE -work-area-backup 0 -rtos auto
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#shutdown OpenOCD daemon when gdb detaches
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$_TARGETNAME configure -event gdb-detach { soft_reset_halt; sleep 5; resume; shutdown }
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m3 reset_config srst
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#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# script for stm32
|
||||
|
||||
source [find mico-os/makefiles/OpenOCD/interface/swj-dp.tcl]
|
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source [find mico-os/makefiles/OpenOCD/mem_helper.tcl]
|
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set CHIP_FLASH_START 0x08000000
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set CHIP_RAM_START 0x20000000
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
|
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
|
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adapter_khz 1000
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
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|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0008
|
||||
# Section 26.6.3
|
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set _CPUTAPID 0x3ba00477
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
if { [info exists BSTAPID ] } {
|
||||
# FIXME this never gets used to override defaults...
|
||||
set _BSTAPID $BSTAPID
|
||||
} else {
|
||||
# See STM Document RM0008
|
||||
# Section 29.6.2
|
||||
# Low density devices, Rev A
|
||||
set _BSTAPID1 0x06412041
|
||||
# Medium density devices, Rev A
|
||||
set _BSTAPID2 0x06410041
|
||||
# Medium density devices, Rev B and Rev Z
|
||||
set _BSTAPID3 0x16410041
|
||||
set _BSTAPID4 0x06420041
|
||||
# High density devices, Rev A
|
||||
set _BSTAPID5 0x06414041
|
||||
# Connectivity line devices, Rev A and Rev Z
|
||||
set _BSTAPID6 0x06418041
|
||||
# XL line devices, Rev A
|
||||
set _BSTAPID7 0x06430041
|
||||
}
|
||||
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
|
||||
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
|
||||
-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
|
||||
-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys $CHIP_RAM_START -work-area-size $_WORKAREASIZE -work-area-backup 0 -rtos auto
|
||||
|
||||
#shutdown OpenOCD daemon when gdb detaches
|
||||
$_TARGETNAME configure -event gdb-detach { soft_reset_halt; sleep 5; resume; shutdown }
|
||||
|
||||
# flash size will be probed
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m3 reset_config srst
|
||||
|
||||
@@ -1,36 +1,36 @@
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
#gdb_port pipe
|
||||
gdb_port 3333
|
||||
#tcl_port 6666
|
||||
|
||||
#swj_mode 2
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
#jtag_khz 1000
|
||||
reset halt
|
||||
#halt
|
||||
|
||||
#setup STM32 pll
|
||||
mww 0x40022000 0x32
|
||||
mww 0x40021004 0x3c0400
|
||||
mww 0x40021000 0x01000883
|
||||
sleep 10
|
||||
mww 0x40021004 0x3c0402
|
||||
sleep 10
|
||||
jtag_khz 6000
|
||||
|
||||
#clear RAM so that the rtos awareness does not detect threads left in memory from previous run
|
||||
mww 0x20000000 0x00000000 0x4000
|
||||
|
||||
#jtag_khz 1000
|
||||
#verify_ircapture disable
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
#gdb_port pipe
|
||||
gdb_port 3333
|
||||
#tcl_port 6666
|
||||
|
||||
#swj_mode 2
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
#jtag_khz 1000
|
||||
reset halt
|
||||
#halt
|
||||
|
||||
#setup STM32 pll
|
||||
mww 0x40022000 0x32
|
||||
mww 0x40021004 0x3c0400
|
||||
mww 0x40021000 0x01000883
|
||||
sleep 10
|
||||
mww 0x40021004 0x3c0402
|
||||
sleep 10
|
||||
jtag_khz 6000
|
||||
|
||||
#clear RAM so that the rtos awareness does not detect threads left in memory from previous run
|
||||
mww 0x20000000 0x00000000 0x4000
|
||||
|
||||
#jtag_khz 1000
|
||||
#verify_ircapture disable
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
init
|
||||
reset halt
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
init
|
||||
reset halt
|
||||
|
||||
@@ -1,15 +1,15 @@
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
gdb_port 3333
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
gdb_port 3333
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
init
|
||||
reset halt
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
init
|
||||
reset halt
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
gdb_port 3333
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
#
|
||||
# UNPUBLISHED PROPRIETARY SOURCE CODE
|
||||
# Copyright (c) 2016 MXCHIP Inc.
|
||||
#
|
||||
# The contents of this file may not be disclosed to third parties, copied or
|
||||
# duplicated in any form, in whole or in part, without the prior written
|
||||
# permission of MXCHIP Corporation.
|
||||
#
|
||||
# default ports
|
||||
telnet_port 4444
|
||||
gdb_port 3333
|
||||
gdb_memory_map enable
|
||||
|
||||
init
|
||||
|
||||
Reference in New Issue
Block a user