From 0aaf4c6baba5fd1d7c915f39cef5fb9ac8817675 Mon Sep 17 00:00:00 2001 From: antirez Date: Thu, 14 Mar 2024 23:50:27 +0100 Subject: [PATCH] Play with different LUTs for different refesh times. --- uc8151.py | 161 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 2 deletions(-) diff --git a/uc8151.py b/uc8151.py index 0a0780c..1914892 100644 --- a/uc8151.py +++ b/uc8151.py @@ -211,9 +211,15 @@ class UC8151: self.write(CMD_PSR,psr_settings) + # Set the lookup tables depending on the speed. + self.set_waveform_lut() + # Here we set the voltage levels that are used for the low-high # transitions states, driven by the waveforms provided in the # lookup tables for refresh. + # + # The VCOM_DC is left to the default of -0.10v, since + # CMD_VDCS is not given. self.write(CMD_PWR, \ [VDS_INTERNAL|VDG_INTERNAL, VCOM_VD|VGHL_16V, @@ -256,6 +262,150 @@ class UC8151: self.write(CMD_POF) self.wait_ready() + # Set the lookup tables used during the display refresh. + # We have a table for each transition possibile: + # white -> white + # white -> black + # black -> black + # black -> white + # and a final table that controls the VCOM voltage. + # + # The update process happens in phases, each 6 rows of each + # table tells the display how to set each pixel based on the + # transition (WW, WB, BB, BW) and VCOM in each phase. + # VCOM is different and explained later, but for the first four + # tables, this is how to interpret them. For instance the + # lookup for WW in turbo speed has the first phase set to: + # + # 0x54, 0x01, 0x01, 0x02, 0x00, 0x01 + # + # The first byte must be read as four two bits integers: + # + # 0x54 is: 01|01|01|00 + # + # Where each 2 bit number menas: + # 00 - Put to ground + # 01 - Put to VDH voltage (11v in our config) + # 10 - Put to VDL voltage (-11v in our config) + # 11 - Not used. + # + # Then the next four bytes in the row mean how many + # "frames" (the refresh tick time, less than 1ms) we + # hold a given state. + # So in the above case: hold pixel at VDH for 1 frame, then + # again VDH for 1 frame, and again, the last entry says 0 frames + # so it's not used. The final number in the row, 0x01, means + # that this sequence must be repeated just once. If it was 2 + # the sequence would repeat 2 times and so forth. + # + # The VCOM table is similar, but the bits meaning is different: + # 00 - Put VCOM to VCM_DC voltage + # 01 - Put VCOM to VDH+VCM_DC voltage (see PWR register config) + # 10 - Put VCOM to VDL+VCM_DC voltage + # 11 - Floating + # + # The meaning of the additional two bytes in the VCOM table + # apparently is the following (but I'm not sure what it means): + # first additional byte: ST_XON, if a (1<