mirror of
https://github.com/pengwon/epd42.git
synced 2025-12-09 16:18:12 +08:00
upgrade to sdk12
This commit is contained in:
Shuanglei Tao
@@ -1,9 +0,0 @@
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#ifndef EPD_BSP_H__
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#define EPD_BSP_H__
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#define RX_PIN_NUMBER 0
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#define TX_PIN_NUMBER 6
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#define RTS_PIN_NUMBER 0
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#define CTS_PIN_NUMBER 0
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#endif
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@@ -1,341 +0,0 @@
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
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||||
*
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||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
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||||
*
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||||
*/
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#ifndef NRF_DRV_CONFIG_H
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#define NRF_DRV_CONFIG_H
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/* CLOCK */
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#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
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#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LF_SRC_Xtal
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#define CLOCK_CONFIG_LF_RC_CAL_INTERVAL RC_2000MS_CALIBRATION_INTERVAL
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#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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/* GPIOTE */
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#define GPIOTE_ENABLED 1
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#if (GPIOTE_ENABLED == 1)
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#define GPIOTE_CONFIG_USE_SWI_EGU false
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#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
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#endif
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/* TIMER */
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#define TIMER0_ENABLED 0
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#if (TIMER0_ENABLED == 1)
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#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
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#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER0_INSTANCE_INDEX 0
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#endif
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#define TIMER1_ENABLED 0
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#if (TIMER1_ENABLED == 1)
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#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
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#endif
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#define TIMER2_ENABLED 0
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#if (TIMER2_ENABLED == 1)
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#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER3_ENABLED 0
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#if (TIMER3_ENABLED == 1)
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#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER4_ENABLED 0
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#if (TIMER4_ENABLED == 1)
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#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
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/* RTC */
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#define RTC0_ENABLED 0
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#if (RTC0_ENABLED == 1)
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#define RTC0_CONFIG_FREQUENCY 32678
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#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC0_CONFIG_RELIABLE false
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#define RTC0_INSTANCE_INDEX 0
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#endif
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#define RTC1_ENABLED 0
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#if (RTC1_ENABLED == 1)
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#define RTC1_CONFIG_FREQUENCY 32768
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#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC1_CONFIG_RELIABLE false
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#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
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#endif
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#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED)
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#define NRF_MAXIMUM_LATENCY_US 2000
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/* RNG */
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#define RNG_ENABLED 0
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#if (RNG_ENABLED == 1)
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#define RNG_CONFIG_ERROR_CORRECTION true
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#define RNG_CONFIG_POOL_SIZE 8
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#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#endif
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/* SPI */
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#define SPI0_ENABLED 1
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#if (SPI0_ENABLED == 1)
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#define SPI0_USE_EASY_DMA 0
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#define SPI0_CONFIG_SCK_PIN 2
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#define SPI0_CONFIG_MOSI_PIN 3
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#define SPI0_CONFIG_MISO_PIN 4
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#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI0_INSTANCE_INDEX 0
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#endif
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#define SPI1_ENABLED 0
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#if (SPI1_ENABLED == 1)
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#define SPI1_USE_EASY_DMA 0
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#define SPI1_CONFIG_SCK_PIN 2
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#define SPI1_CONFIG_MOSI_PIN 3
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#define SPI1_CONFIG_MISO_PIN 4
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#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
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#endif
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#define SPI2_ENABLED 0
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#if (SPI2_ENABLED == 1)
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#define SPI2_USE_EASY_DMA 0
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#define SPI2_CONFIG_SCK_PIN 2
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#define SPI2_CONFIG_MOSI_PIN 3
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#define SPI2_CONFIG_MISO_PIN 4
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#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
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#endif
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#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
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/* SPIS */
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#define SPIS0_ENABLED 0
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#if (SPIS0_ENABLED == 1)
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#define SPIS0_CONFIG_SCK_PIN 2
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#define SPIS0_CONFIG_MOSI_PIN 3
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#define SPIS0_CONFIG_MISO_PIN 4
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#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPIS0_INSTANCE_INDEX 0
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#endif
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#define SPIS1_ENABLED 0
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#if (SPIS1_ENABLED == 1)
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#define SPIS1_CONFIG_SCK_PIN 2
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#define SPIS1_CONFIG_MOSI_PIN 3
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#define SPIS1_CONFIG_MISO_PIN 4
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#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
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#endif
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#define SPIS2_ENABLED 0
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#if (SPIS2_ENABLED == 1)
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#define SPIS2_CONFIG_SCK_PIN 2
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#define SPIS2_CONFIG_MOSI_PIN 3
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#define SPIS2_CONFIG_MISO_PIN 4
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#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
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#endif
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#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
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/* UART */
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#define UART0_ENABLED 1
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#if (UART0_ENABLED == 1)
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#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
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#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
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#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_38400
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#define UART0_CONFIG_PSEL_TXD 0
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#define UART0_CONFIG_PSEL_RXD 0
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#define UART0_CONFIG_PSEL_CTS 0
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#define UART0_CONFIG_PSEL_RTS 0
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#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#ifdef NRF52
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#define UART0_CONFIG_USE_EASY_DMA false
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//Compile time flag
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#define UART_EASY_DMA_SUPPORT 1
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#define UART_LEGACY_SUPPORT 1
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#endif //NRF52
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#endif
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#define TWI0_ENABLED 0
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#if (TWI0_ENABLED == 1)
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#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
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#define TWI0_CONFIG_SCL 0
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#define TWI0_CONFIG_SDA 1
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#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TWI0_INSTANCE_INDEX 0
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#endif
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#define TWI1_ENABLED 1
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#if (TWI1_ENABLED == 1)
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#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
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#define TWI1_CONFIG_SCL 0
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#define TWI1_CONFIG_SDA 1
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#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
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#endif
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#define TWI_COUNT (TWI0_ENABLED+TWI1_ENABLED)
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/* TWIS */
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#define TWIS0_ENABLED 0
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#if (TWIS0_ENABLED == 1)
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#define TWIS0_CONFIG_ADDR0 0
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#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
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#define TWIS0_CONFIG_SCL 0
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#define TWIS0_CONFIG_SDA 1
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#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TWIS0_INSTANCE_INDEX 0
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#endif
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#define TWIS1_ENABLED 0
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#if (TWIS1_ENABLED == 1)
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#define TWIS1_CONFIG_ADDR0 0
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#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
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#define TWIS1_CONFIG_SCL 0
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#define TWIS1_CONFIG_SDA 1
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#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
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#endif
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#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
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/* For more documentation see nrf_drv_twis.h file */
|
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#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
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/* For more documentation see nrf_drv_twis.h file */
|
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#define TWIS_NO_SYNC_MODE 0
|
||||
/**
|
||||
* @brief Definition for patching PAN problems
|
||||
*
|
||||
* Set this definition to nonzero value to patch anomalies
|
||||
* from MPW3 - first lunch microcontroller.
|
||||
*
|
||||
* Concerns:
|
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* - PAN-29: TWIS: incorrect bits in ERRORSRC
|
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* - PAN-30: TWIS: STOP task does not work as expected
|
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*/
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#define NRF_TWIS_PATCH_FOR_MPW3 1
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||||
|
||||
|
||||
/* QDEC */
|
||||
#define QDEC_ENABLED 0
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|
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#if (QDEC_ENABLED == 1)
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#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
|
||||
#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
|
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#define QDEC_CONFIG_PIO_A 1
|
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#define QDEC_CONFIG_PIO_B 2
|
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#define QDEC_CONFIG_PIO_LED 3
|
||||
#define QDEC_CONFIG_LEDPRE 511
|
||||
#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
|
||||
#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#define QDEC_CONFIG_DBFEN false
|
||||
#define QDEC_CONFIG_SAMPLE_INTEN false
|
||||
#endif
|
||||
|
||||
/* SAADC */
|
||||
#define SAADC_ENABLED 0
|
||||
|
||||
#if (SAADC_ENABLED == 1)
|
||||
#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
|
||||
#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
|
||||
#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#endif
|
||||
|
||||
/* LPCOMP */
|
||||
#define LPCOMP_ENABLED 0
|
||||
|
||||
#if (LPCOMP_ENABLED == 1)
|
||||
#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
|
||||
#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
|
||||
#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
|
||||
#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
|
||||
#endif
|
||||
|
||||
/* WDT */
|
||||
#define WDT_ENABLED 0
|
||||
|
||||
#if (WDT_ENABLED == 1)
|
||||
#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
|
||||
#define WDT_CONFIG_RELOAD_VALUE 2000
|
||||
#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
|
||||
#endif
|
||||
|
||||
/* SWI EGU */
|
||||
#ifdef NRF52
|
||||
#define EGU_ENABLED 0
|
||||
#endif
|
||||
|
||||
|
||||
#include "nrf_drv_config_validation.h"
|
||||
|
||||
#endif // NRF_DRV_CONFIG_H
|
||||
@@ -1,78 +0,0 @@
|
||||
/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
|
||||
*
|
||||
* The information contained herein is property of Nordic Semiconductor ASA.
|
||||
* Terms and conditions of usage are described in detail in NORDIC
|
||||
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
*
|
||||
* Licensees are granted free, non-transferable use of the information. NO
|
||||
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
* the file.
|
||||
*
|
||||
*/
|
||||
|
||||
/** @cond To make doxygen skip this file */
|
||||
|
||||
/** @file
|
||||
* This header contains defines with respect persistent storage that are specific to
|
||||
* persistent storage implementation and application use case.
|
||||
*/
|
||||
#ifndef PSTORAGE_PL_H__
|
||||
#define PSTORAGE_PL_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "nrf.h"
|
||||
|
||||
static __INLINE uint16_t pstorage_flash_page_size()
|
||||
{
|
||||
return (uint16_t)NRF_FICR->CODEPAGESIZE;
|
||||
}
|
||||
|
||||
#define PSTORAGE_FLASH_PAGE_SIZE pstorage_flash_page_size() /**< Size of one flash page. */
|
||||
#define PSTORAGE_FLASH_EMPTY_MASK 0xFFFFFFFF /**< Bit mask that defines an empty address in flash. */
|
||||
|
||||
#ifdef NRF51
|
||||
#define BOOTLOADER_ADDRESS (NRF_UICR->BOOTLOADERADDR)
|
||||
#elif defined NRF52
|
||||
#define BOOTLOADER_ADDRESS (PSTORAGE_FLASH_EMPTY_MASK)
|
||||
#endif
|
||||
|
||||
static __INLINE uint32_t pstorage_flash_page_end()
|
||||
{
|
||||
uint32_t bootloader_addr = BOOTLOADER_ADDRESS;
|
||||
|
||||
return ((bootloader_addr != PSTORAGE_FLASH_EMPTY_MASK) ?
|
||||
(bootloader_addr/ PSTORAGE_FLASH_PAGE_SIZE) : NRF_FICR->CODESIZE);
|
||||
}
|
||||
|
||||
#define PSTORAGE_FLASH_PAGE_END pstorage_flash_page_end()
|
||||
|
||||
#define PSTORAGE_NUM_OF_PAGES 1 /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */
|
||||
#define PSTORAGE_MIN_BLOCK_SIZE 0x0010 /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */
|
||||
|
||||
#define PSTORAGE_DATA_START_ADDR ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES - 1) \
|
||||
* PSTORAGE_FLASH_PAGE_SIZE) /**< Start address for persistent data, configurable according to system requirements. */
|
||||
#define PSTORAGE_DATA_END_ADDR ((PSTORAGE_FLASH_PAGE_END - 1) * PSTORAGE_FLASH_PAGE_SIZE) /**< End address for persistent data, configurable according to system requirements. */
|
||||
#define PSTORAGE_SWAP_ADDR PSTORAGE_DATA_END_ADDR /**< Top-most page is used as swap area for clear and update. */
|
||||
|
||||
#define PSTORAGE_MAX_BLOCK_SIZE PSTORAGE_FLASH_PAGE_SIZE /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */
|
||||
#define PSTORAGE_CMD_QUEUE_SIZE 10 /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */
|
||||
|
||||
|
||||
/** Abstracts persistently memory block identifier. */
|
||||
typedef uint32_t pstorage_block_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t module_id; /**< Module ID.*/
|
||||
pstorage_block_t block_id; /**< Block ID.*/
|
||||
} pstorage_handle_t;
|
||||
|
||||
typedef uint16_t pstorage_size_t; /** Size of length and offset fields. */
|
||||
|
||||
/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */
|
||||
void pstorage_sys_event_handler (uint32_t sys_evt);
|
||||
|
||||
#endif // PSTORAGE_PL_H__
|
||||
|
||||
/** @} */
|
||||
/** @endcond */
|
||||
3738
config/sdk_config.h
Normal file
3738
config/sdk_config.h
Normal file
File diff suppressed because it is too large
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