diff --git a/PINOUT/Parallel-26PIN.md b/PINOUT/Parallel-26PIN.md new file mode 100644 index 0000000..4dc5878 --- /dev/null +++ b/PINOUT/Parallel-26PIN.md @@ -0,0 +1,47 @@ +# EPD PINOUT (26 PIN) + +- GDE043A2 +- GDE043A3 + +## Reference design + +N/A + +## Connector + +- FH12-26S-0.5SH + +## Definition + +| # | Type | Name | Description | Note | +| --: | ---: | -----------------: | :------------------------------------ | :------------ | +| 1 | PWR | VNEG | Negative power supply source driver | Power Supply | +| 2 | PWR | VPOS | Positive power supply source driver | Power Supply | +| 3 | GND | VSS | Ground | | +| 4 | PWR | VDD | Digital power supply driver | Power Supply | +| 5 | | XCK | Clock source driver | Source driver | +| 6 | | XLE | Latch enable source driver | Source driver | +| 7 | | XOE | Output enable source driver | Source driver | +| 8 | | SHR | Shift direction source driver | Source driver | +| 9 | | SPH | Start pulse source driver | Source driver | +| 10 | I | D0 | Data signal source driver | Source driver | +| 11 | I | D1 | Data signal source driver | Source driver | +| 12 | I | D2 | Data signal source driver | Source driver | +| 13 | I | D3 | Data signal source driver | Source driver | +| 14 | I | D4 | Data signal source driver | Source driver | +| 15 | I | D5 | Data signal source driver | Source driver | +| 16 | I | D6 | Data signal source driver | Source driver | +| 17 | I | D7 | Data signal source driver | Source driver | +| 18 | PWR | VCOM | Common connection | | +| 19 | PWR | VGH | Positive power supply gate driver | Power Supply | +| 20 | PWR | VGL | Negative power supply gate driver | Power Supply | +| 21 | | GMODE1 | Output mode selection gate driver (H) | | +| 22 | | GMODE2 | Output mode selection gate driver (H) | | +| 23 | | L/R | Shift direction gate driver | | +| 24 | | STV | Start pulse gate driver | | +| 25 | | CPV | Shift click input | | +| 26 | PWR | VBORDER | Border connection | | + +## Note + +N/A diff --git a/PINOUT/Parallel-34PIN.md b/PINOUT/Parallel-34PIN.md new file mode 100644 index 0000000..5590409 --- /dev/null +++ b/PINOUT/Parallel-34PIN.md @@ -0,0 +1,60 @@ +# EPD PINOUT (34 PIN) + +- GDEW060C01 +- GDE060BA +- GDE060F3 +- GDEW078C01 +- GDEW080T5 +- GDEP097TC2 +- GDEP312TT2-D + +## Reference design + +N/A + +## Connector + +- FH12-34S-0.5SH + +## Definition + +| # | Type | Name | Description | Note | +| --: | ---: | -----------------: | :---------------------------------- | :------------ | +| 1 | PWR | VNEG | Negative power supply source driver | Power Supply | +| 2 | PWR | VGL | Negative power supply gate driver | Power Supply | +| 3 | GND | VSS | Ground | | +| 4 | NC | NC | No connection | | +| 5 | NC | NC | No connection | | +| 6 | PWR | VDD | Digital power supply driver | Power Supply | +| 7 | GND | VSS | Ground | | +| 8 | | XCL | Clock source driver | Source driver | +| 9 | GND | VSS | Ground | | +| 10 | | XLE | Latch enable source driver | Source driver | +| 11 | | XOE | Output enable source driver | Source driver | +| 12 | | XSTL | Start pulse gate driver | | +| 13 | I | D0 | Data signal source driver | Source driver | +| 14 | I | D1 | Data signal source driver | Source driver | +| 15 | I | D2 | Data signal source driver | Source driver | +| 16 | I | D3 | Data signal source driver | Source driver | +| 17 | I | D4 | Data signal source driver | Source driver | +| 18 | I | D5 | Data signal source driver | Source driver | +| 19 | I | D6 | Data signal source driver | Source driver | +| 20 | I | D7 | Data signal source driver | Source driver | +| 21 | PWR | VCOM | Common connection | | +| 22 | NC | NC | No connection | | +| 23 | NC | NC | No connection | | +| 24 | NC | NC | No connection | | +| 25 | NC | NC | No connection | | +| 26 | GND | VSS | Ground | | +| 27 | | GMODE1 | Output mode selection gate driver | | +| 28 | | CKV | Clock gate driver | | +| 29 | | SPV | Start pulse gate driver | | +| 30 | NC | NC | No connection | | +| 31 | PWR | VBORDER | Border connection | | +| 32 | GND | VSS | Ground | | +| 33 | PWR | VPOS | Positive power supply source driver | Power Supply | +| 34 | PWR | VGH | Positive power supply gate driver | Power Supply | + +## Note + +N/A diff --git a/PINOUT/README.md b/PINOUT/README.md new file mode 100644 index 0000000..4ec2a9b --- /dev/null +++ b/PINOUT/README.md @@ -0,0 +1,15 @@ +# EPD PINOUT + +## SPI + +- [24 PIN](SPI-24PIN.md) - Cover 90+ percentage EPD screen + +- [30 PIN](SPI-30PIN.md) + +- [60 PIN](SPI-60PIN.md) - Cascade display + +## Parallel + +- [26 PIN](Parallel-26PIN.md) + +- [34 PIN](Parallel-34PIN.md) diff --git a/PINOUT.md b/PINOUT/SPI-24PIN.md similarity index 75% rename from PINOUT.md rename to PINOUT/SPI-24PIN.md index 5b93939..063780f 100644 --- a/PINOUT.md +++ b/PINOUT/SPI-24PIN.md @@ -1,4 +1,4 @@ -# EPD General PINOUT +# EPD PINOUT (24 PIN) ## Reference design @@ -9,54 +9,45 @@ ## Connector -| PIN# | Connector | Interface | -| ---- | -------------- | --------- | -| 24 | FH12-24S-0.5SH | SPI | -| 34 | FH12-34S-0.5SH | SPI | +- FH12-24S-0.5SH +- FH12-34S-0.5SH -## 24PIN Definition +## Definition | # | Type | Name | Description | Note | | --: | ---: | -----------------: | :----------------------------------------- | :------------------------- | -| 01 | NC | NC | Keep Open | | -| 02 | O | GDR | N-Channel MOSFET gate drive control | | +| 01 | NC | NC | No connection | | +| 02 | O | GDR | N-Channel MOS-FET gate drive control | | | 03 | O | RESE | Current sense input for the control loop | [RESE](#rese) | -| 04 | C | VGL | Negative gate driving voltage | | -| 05 | C | VGH | Positive gate driving voltage | | +| 04 | PWR | VGL | Negative gate driving voltage | Driving voltage | +| 05 | PWR | VGH | Positive gate driving voltage | Driving voltage | | 06 | O | TSCL | (I2C) Sensor Clock | [Digital Temperature][dt] | | 07 | I/O | TSDA | (I2C) Sensor Data | [Digital Temperature][dt] | | 08 | I | BS1 | Bus selection | [BS1](#bs1) | | 09 | O | BUSY | Busy state output | [BUSY](#busy) | -| 10 | I | RES# | Reset | [SPI](#spi), [RES#](#resn) | +| 10 | I | RES# | Global reset pin | [SPI](#spi), [RES#](#resn) | | 11 | I | D/C# | (SPI) Data/Command control | [SPI](#spi), [D/C#](#dcn) | -| 12 | I | CS# | (SPI SS) Chip select input | [SPI](#spi), [CS#](#csn) | +| 12 | I | CS# | (SPI SS) Chip select | [SPI](#spi), [CS#](#csn) | | 13 | I/O | D0 | (SPI SCLK) Serial clock | [SPI](#spi) | | 14 | I/O | D1 | (SPI MOSI) Serial data in | [SPI](#spi) | -| 15 | I | VDDIO | (SPI VCC) Power Supply for interface logic | | -| 16 | I | VDI | Power Supply for the chip | | -| 17 | | VSS | (GND) Ground | | -| 18 | C | VDD | Corelogic power | | -| 19 | C | VPP | Power Supply for OTP programming | | -| 20 | C | VSH | Positive source driving voltage | | -| 21 | C | PRE VGH | Power Supply for `VGH` and `VSH` | | -| 22 | C | VSL | Negative source driving voltage | | -| 23 | C | PRE VGL | Power Supply for `VCOM`, `VGL` and `VSL` | | -| 24 | C | VCOM | `VCOM` driving voltage | | +| 15 | I | VDDIO | (SPI VCC) Power Supply for interface logic | Power Supply | +| 16 | I | VDI | Power Supply for the chip | Power Supply | +| 17 | GND | VSS | (GND) Ground | | +| 18 | PWR | VDD | Corelogic power | | +| 19 | PWR | VPP | Power Supply for OTP programming | Power Supply | +| 20 | PWR | VSH | Positive source driving voltage | Driving voltage | +| 21 | PWR | PRE VGH | Power Supply for `VGH` and `VSH` | Power Supply | +| 22 | PWR | VSL | Negative source driving voltage | Driving voltage | +| 23 | PWR | PRE VGL | Power Supply for `VCOM`, `VGL` and `VSL` | Power Supply | +| 24 | PWR | VCOM | `VCOM` driving voltage | Driving voltage | -```plain -I: Input -O: Output -C: PWR -NC: No Connection -``` - -[dt]: sensors/lm75.md +[dt]: ../sensors/lm75.md ## Note ### CSn -This pin (`CS#`) is the chip select input connecting to the MCU. +This pin (`CS#`) is the Chip select connecting to the MCU.
The chip is enabled for MCU communication only when `CS#` is pulled _LOW_. ### D/Cn diff --git a/PINOUT/SPI-30PIN.md b/PINOUT/SPI-30PIN.md new file mode 100644 index 0000000..e41d139 --- /dev/null +++ b/PINOUT/SPI-30PIN.md @@ -0,0 +1,55 @@ +# EPD PINOUT (30 PIN) + +- GDEW0102I3F +- GDEW0102I4FC +- GDEW0102T4 + +## Reference design + +- + +## Connector + +- FH12-30S-0.5SH + +## Definition + +| # | Type | Name | Description | Note | +| --: | ---: | ---------------: | :------------------------------ | :------------------------ | +| 1 | PWR | VPP | OTP program power | | +| 2 | PWR | GND | (GND) Digital ground | | +| 3 | PWR | VDD | Digital power | | +| 4 | I/O | SDA | (SPI MOSI) Serial data in | [SPI][spi] | +| 5 | I | SCL | (SPI SCLK) Serial clock | [SPI][spi] | +| 6 | I | CS# | (SPI SS) Chip select | [SPI][spi], [CS#][csn] | +| 7 | I | D/C# | (SPI) Data/Command control | [SPI][spi], [D/C#][dcn] | +| 8 | I | RES# | Global reset pin | [SPI][spi], [RES#][resn] | +| 9 | O | BUSY | Busy state output | [BUSY][busy] | +| 10 | I | BS1 | Bus selection | [BS1][bs1] | +| 11 | PWR | VDD | (SPI VDD) Digital power input | | +| 12 | PWR | VDL | Negative source driving voltage | Driving voltage | +| 13 | PWR | VDH | Positive source driving voltage | Driving voltage | +| 14 | PWR | VGH | Positive gate driving voltage | Driving voltage | +| 15 | PWR | VGL | Negative gate driving voltage | Driving voltage | +| 16 | PWR | C6N | Negative side | Capacitor connecting pins | +| 17 | PWR | C6P | Pegative side | Capacitor connecting pins | +| 18 | PWR | C5N | Negative side | Capacitor connecting pins | +| 19 | PWR | C5P | Pegative side | Capacitor connecting pins | +| 20 | PWR | C4N | Negative side | Capacitor connecting pins | +| 21 | PWR | C4P | Pegative side | Capacitor connecting pins | +| 22 | PWR | C3N | Negative side | Capacitor connecting pins | +| 23 | PWR | C3P | Pegative side | Capacitor connecting pins | +| 24 | PWR | C2N | Negative side | Capacitor connecting pins | +| 25 | PWR | C2P | Pegative side | Capacitor connecting pins | +| 26 | PWR | C1N | Negative side | Capacitor connecting pins | +| 27 | PWR | C1P | Pegative side | Capacitor connecting pins | +| 28 | PWR | VCOML | Negative pumping voltage | Internal use | +| 29 | PWR | VCOMH | Positive pumping voltage | Internal use | +| 30 | O | VCOM | `VCOM` output | | + +[spi]: SPI-24PIN.md#spi +[csn]: SPI-24PIN.md#csn +[dcn]: SPI-24PIN.md#dcn +[resn]: SPI-24PIN.md#resn +[busy]: SPI-24PIN.md#busy +[bs1]: SPI-24PIN.md#bs1 diff --git a/PINOUT/SPI-60PIN.md b/PINOUT/SPI-60PIN.md new file mode 100644 index 0000000..5dbeec5 --- /dev/null +++ b/PINOUT/SPI-60PIN.md @@ -0,0 +1,56 @@ +# EPD PINOUT (30x2 PIN) + +- GDEW1248C63 +- GDEW1248T3 +- GDEW1248Z95 + +## Reference design + +- + +## Connector + +- FH12-30S-0.5SH + +## Definition + +| # | Type | Name | Side | Description | Note | +| --: | ---: | -----------------------------: | ----- | :---------------------------------------- | :----------------------- | +| 1 | I | CS# | M1/M2 | (SPI SS) Chip select | | +| 2 | O | GDR | M1/M2 | N-Channel MOS-FET gate drive control | | +| 3 | P | RESE | M1/M2 | Current sense input for control loop | [RESE][rese] | +| 4 | P | VSHR | M1/M2 | Positive source driving voltage for _RED_ | Driving voltage | +| 5 | O | TSCL | | (I2C) Sensor Clock | | +| 6 | I/O | TSDA | | (I2C) Sensor Data | | +| 7 | I | BS1 | | Bus selection | [BS1][bs1] | +| 8 | O | BUSY# | M1/M2 | Busy state output | [BUSY][busy] | +| 9 | I | RST# | | Global reset pin | [SPI][spi], [RES#][resn] | +| 10 | I | D/C# | | (SPI) Data/Command control | [SPI][spi], [D/C#][dcn] | +| 11 | I | CS# | S1/S2 | (SPI SS) Chip select | [SPI][spi] | +| 12 | I | SCL | | (SPI SCLK) Serial clock | [SPI][spi] | +| 13 | I/O | SDA | | (SPI MOSI) Serial data in | [SPI][spi] | +| 14 | I/O | LSYNC | M1/M2 | 2 + 2 Cascade Sync Signal | | +| 15 | I/O | M1/M2SYNC | M1/M2 | 2 + 2 Cascade Sync Signal | | +| 16 | I/O | M2/M1SYNC | M1/M2 | 2 + 2 Cascade Sync Signal | | +| 17 | PWR | VDDIO | M1/M2 | (SPI VCC) IO voltage supply | | +| 18 | PWR | VDD | M1/M2 | Corelogic power | | +| 19 | PWR | VSS | M1/M2 | (GND) Digital ground | | +| 20 | PWR | VDD1.8V | M1/M2 | (1.8V) Voltage input & output | | +| 21 | PWR | VOTP7.5V | M1/M2 | (7.5V) OTP program power | | +| 22 | PWR | VSH | M1/M2 | Positive source driving voltage | Driving voltage | +| 23 | PWR | VGH | M1/M2 | Positive gate driving voltage | Driving voltage | +| 24 | PWR | VSL | M1/M2 | Negative source driving voltage | Driving voltage | +| 25 | PWR | VGL | M1/M2 | Negative gate driving voltage | Driving voltage | +| 26 | O | VCOM | M1/M2 | `VCOM` output | | +| 27 | O | BUSY# | S1/S2 | Busy state output | | +| 28 | PWR | VSHR | S1/S2 | Positive source driving voltage for _RED_ | Driving voltage | +| 29 | PWR | VSH | S1/S2 | Positive source driving voltage | Driving voltage | +| 30 | PWR | VSL | S1/S2 | Positive gate driving voltage | Driving voltage | + +[bs1]: SPI-24PIN.md#bs1 +[busy]: SPI-24PIN.md#busy +[csn]: SPI-24PIN.md#csn +[dcn]: SPI-24PIN.md#dcn +[rese]: SPI-24PIN.md#rese +[resn]: SPI-24PIN.md#resn +[spi]: SPI-24PIN.md#spi diff --git a/README.md b/README.md index 5aa3c13..4581238 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ > Electronic Paper Display - [Dot matrix font family](font-family.md) -- [General PINOUT Definition](PINOUT.md) +- [PINOUT Definition](PINOUT) - [List of Display](epd-display.csv) - [List of Driver IC](https://cursedhardware.github.io/epd-driver-ic/) - [List of Sensor](sensors) diff --git a/epd-display.csv b/epd-display.csv index f4ce1ec..d300879 100644 --- a/epd-display.csv +++ b/epd-display.csv @@ -259,9 +259,9 @@ Good Display,GDEW080T5,EINK,8,B/W,4bpp,1024 x 768,Parallel,34,UC8142 + UC8143, Good Display,GDEP097TC2,EINK,9.7,B/W,4bpp,1200 x 825,Parallel,34,UC8142 + UC8143, Good Display,GDEH116T91,EINK,11.6,B/W/R,,960 x 640,SPI,24,SSD1677, Good Display,GDEH116Z91,EINK,11.6,B/W/R,,960 x 640,SPI,24,SSD1677, -Good Display,GDEW1248C63,EINK,12.48,B/W/Y,2bpp,1304 x 984,SPI,30,IL0326, -Good Display,GDEW1248T3,EINK,12.48,B/W,2bpp,1304 x 984,SPI,30,IL0326,EOL -Good Display,GDEW1248Z95,EINK,12.48,B/W/R,2bpp,1304 x 984,SPI,30,IL0326,EOL +Good Display,GDEW1248C63,EINK,12.48,B/W/Y,2bpp,1304 x 984,SPI,60,IL0326, +Good Display,GDEW1248T3,EINK,12.48,B/W,2bpp,1304 x 984,SPI,60,IL0326,EOL +Good Display,GDEW1248Z95,EINK,12.48,B/W/R,2bpp,1304 x 984,SPI,60,IL0326,EOL Good Display,GDEP312TT2-D,EINK,31.2,B/W,4bpp,2560 x 1440,Parallel,34,UC8142 + UC8143, Holitech,HINK-E0154A05,EINK,1.54,B/W,,200 x 200,SPI,24,SSD1608, Holitech,HINK-E0154A07,EINK,1.54,B/W/R,,152 x 152,SPI,24,SSD1675B,